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| User's Manual, V2.0, April 2004 XC167-16 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units Microcontrollers Never stop thinking. Edition 2004-04 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. User's Manual, V2.0, April 2004 XC167-16 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units Microcontrollers Never stop thinking. XC167 Revision History: Previous Version: Page all Volume 2 (of 2): Peripheral Units V2.0, 2004-04 V1.1, 2002-02 (Draft Manual) V1.0, 2001-04 (Draft Manual) Subjects (major changes since version V1.1) Numerous internal and external contributions have lead to manifold improvements throughout this manual. Typos and detected faults have been corrected, contradictions have been resolved, missing documentation has been added, misleading information has been removed, corporate documentation rules have been applied. Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Template: mc_tmplt_a5.fm / 3 / 2003-09-01 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page This User's Manual consists of two Volumes, "System Units" and "Peripheral Units". For your convenience this table of contents (and also the keyword index) lists both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]). 1 1.1 1.2 1.3 1.4 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2 2.3 2.4 2.5 2.6 2.7 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1] Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . 1-3 [1] Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1] Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1] Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1] Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1] Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1] High Instruction Bandwidth/Fast Execution . . . . . . . . . . . . . . . . . . . 2-4 [1] Powerful Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1] High Performance Branch-, Call-, and Loop-Processing . . . . . . . . . 2-6 [1] Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . 2-7 [1] Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . 2-8 [1] Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1] On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1] On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 [1] Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1] Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1] On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 [1] Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1] Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1] Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1] Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1] Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 [1] Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1] System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1] IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 [1] External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1] Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1] The On-Chip Program Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1] Flash Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 [1] Error Correction and Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . 3-25 [1] Protection and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 [1] Flash Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 [1] Operation Control and Error Handling . . . . . . . . . . . . . . . . . . . . . . 3-35 [1] I-1 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 3.10 3.10.1 3.10.2 3.10.3 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.8 4.8.1 4.8.2 4.8.3 4.9 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 4.9.9 4.9.10 4.10 Program Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMB Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 3-37 [1] 3-38 [1] 3-39 [1] 3-41 [1] Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1] Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1] Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . 4-5 [1] Branch Detection and Branch Prediction Rules . . . . . . . . . . . . . . . . 4-7 [1] Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1] Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1] Instruction Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1] Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . 4-13 [1] Pipeline Conflicts Using Indirect Addressing Modes . . . . . . . . . . . 4-15 [1] Pipeline Conflicts Due to Memory Bandwidth . . . . . . . . . . . . . . . . 4-17 [1] Pipeline Conflicts Caused by CPU-SFR Updates . . . . . . . . . . . . . 4-20 [1] CPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1] Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1] GPR Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1] Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1] Code Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 [1] Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1] Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1] Long Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1] Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 [1] DSP Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 [1] The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 [1] Standard Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 [1] 16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . . 4-61 [1] Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 [1] Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 [1] DSP Data Processing (MAC Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 [1] Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . . 4-66 [1] The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler . . . . . 4-67 [1] Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1] One-bit Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1] The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1] The Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1] The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1] The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . . 4-69 [1] The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 [1] The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 [1] Constant Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74 [1] I-2 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.4.1 6.4.2 6.4.3 Page Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1] Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1] Interrupt Arbitration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 [1] Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1] Operation of the Peripheral Event Controller Channels . . . . . . . . . . 5-18 [1] The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 5-22 [1] PEC Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 [1] Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 5-26 [1] PEC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 [1] Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . 5-29 [1] Context Switching and Saving Status . . . . . . . . . . . . . . . . . . . . . . . . 5-31 [1] Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 [1] External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1] OCDS Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 [1] Service Request Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1] Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 [1] General System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1] System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1] Reset Sources and Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1] Status After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1] Application-Specific Initialization Routine . . . . . . . . . . . . . . . . . . . 6-11 [1] System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 [1] Hardware Configuration in External Start Mode . . . . . . . . . . . . . . 6-18 [1] Default Configuration in Single-Chip Mode . . . . . . . . . . . . . . . . . . 6-23 [1] Reset Behavior Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 [1] Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 [1] Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 [1] Clock Generation and Frequency Control . . . . . . . . . . . . . . . . . . . 6-30 [1] Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 [1] Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1] Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1] Generation of an External Clock Signal . . . . . . . . . . . . . . . . . . . . 6-39 [1] Central System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 [1] Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 [1] Reset Source Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 [1] Peripheral Shutdown Handshake . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1] Debug System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 [1] Register Security Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 [1] Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54 [1] Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54 [1] Reduction of Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 [1] Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 [1] I-3 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 6.5 6.6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 9 9.1 9.2 9.2.1 9.2.1.1 9.2.1.2 9.2.2 9.2.2.1 9.2.2.2 9.2.2.3 9.2.2.4 9.2.2.5 9.2.2.6 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.6.1 9.3.6.2 9.3.7 Page Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 [1] Identification Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64 [1] Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1] Input Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1] Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 [1] Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 [1] PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1] PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 [1] Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 [1] Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 [1] Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 [1] Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50 [1] Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 [1] Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65 [1] Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-72 [1] Port 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-82 [1] Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1] The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1] External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1] Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1] Basic Bus Cycle Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1] Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 [1] Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1] Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] A Phase - CS Change Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] B Phase - Address Setup/ALE Phase . . . . . . . . . . . . . . . . . . . . . 9-7 [1] C Phase - Delay Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] D Phase - Write Data Setup/MUX Tristate Phase . . . . . . . . . . . . 9-7 [1] E Phase - RD/WR Command Phase . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] F Phase - Address/Write Data Hold Phase . . . . . . . . . . . . . . . . . 9-8 [1] Bus Cycle Examples: Fastest Access Cycles . . . . . . . . . . . . . . . . . 9-8 [1] Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1] Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1] The EBC Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 [1] The EBC Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 [1] The Timing Configuration Registers TCONCSx . . . . . . . . . . . . . . 9-15 [1] The Function Configuration Registers FCONCSx . . . . . . . . . . . . . 9-16 [1] The Address Window Selection Registers ADDRSELx . . . . . . . . . 9-18 [1] Definition of Address Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 [1] Address Window Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 [1] Ready Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1] I-4 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 9.3.7.1 9.3.7.2 9.3.7.3 9.3.8 9.3.9 9.3.9.1 9.3.9.2 9.3.9.3 9.3.9.4 9.3.9.5 9.3.10 9.4 9.5 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 11.3.1 11.3.2 11.4 11.4.1 11.5 12 13 14 14.1 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.1.6 14.1.7 14.2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Synchronous/Asynchronous READY . . . . . . . . . . . . . . . . . Combining the READY Function with Predefined Wait States . Access Control to TwinCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization of Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitration Master Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitration Slave Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Lock Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Master Slave Connection . . . . . . . . . . . . . . . . . . . . . . . . Shutdown Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LXBus Access Control and Signal Generation . . . . . . . . . . . . . . . . . EBC Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering the Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exiting Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Choosing the Baudrate for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCDS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cerberus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emulation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 9-21 [1] 9-22 [1] 9-22 [1] 9-23 [1] 9-24 [1] 9-24 [1] 9-24 [1] 9-26 [1] 9-27 [1] 9-27 [1] 9-28 [1] 9-29 [1] 9-29 [1] 10-1 [1] 10-2 [1] 10-4 [1] 10-4 [1] 10-5 [1] 11-1 [1] 11-1 [1] 11-2 [1] 11-3 [1] 11-5 [1] 11-6 [1] 11-7 [1] 11-7 [1] 11-9 [1] Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1] Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1] The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2] Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 [2] GPT1 Core Timer T3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 [2] GPT1 Core Timer T3 Operating Modes . . . . . . . . . . . . . . . . . . . . . 14-8 [2] GPT1 Auxiliary Timers T2/T4 Control . . . . . . . . . . . . . . . . . . . . . 14-15 [2] GPT1 Auxiliary Timers T2/T4 Operating Modes . . . . . . . . . . . . . 14-18 [2] GPT1 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 [2] GPT1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 [2] Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . 14-30 [2] Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 [2] User's Manual I-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.2.6 14.2.7 14.2.8 14.3 15 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.4 16 16.1 16.1.1 16.1.2 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.3 16.4 16.5 16.6 17 17.1 17.2 17.3 17.4 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 GPT2 Core Timer T6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT2 Core Timer T6 Operating Modes . . . . . . . . . . . . . . . . . . . . GPT2 Auxiliary Timer T5 Control . . . . . . . . . . . . . . . . . . . . . . . . GPT2 Auxiliary Timer T5 Operating Modes . . . . . . . . . . . . . . . . . GPT2 Register CAPREL Operating Modes . . . . . . . . . . . . . . . . . GPT2 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT2 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . Interfaces of the GPT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 14-33 [2] 14-37 [2] 14-40 [2] 14-42 [2] 14-46 [2] 14-51 [2] 14-54 [2] 14-55 [2] 14-56 [2] Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2] Defining the RTC Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 [2] RTC Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [2] RTC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [2] 48-bit Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2] System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2] Cyclic Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2] RTC Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [2] The Analog/Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2] Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2] Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2] Enhanced Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [2] ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [2] Fixed Channel Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [2] Auto Scan Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 [2] Wait for Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 [2] Channel Injection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 [2] Automatic Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 [2] Conversion Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 [2] A/D Converter Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 [2] Interfaces of the ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [2] Capture/Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2] The CAPCOM Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [2] CAPCOM Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [2] Capture/Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [2] Capture Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [2] Compare Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [2] Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2] Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2] Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2] Compare Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2] Double-Register Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . 17-22 [2] I-6 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 17.6 17.7 17.8 17.9 17.10 17.11 18 18.1 18.1.1 18.1.2 18.1.3 18.1.4 18.1.5 18.2 18.2.1 18.2.2 18.3 18.4 18.5 18.5.1 18.5.2 18.5.3 18.5.4 18.6 18.7 18.8 18.9 18.10 18.11 19 19.1 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.2.8 19.3 Compare Output Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Staggered and Non-Staggered Operation . . . . . . . . . . . . . . . . . . . . CAPCOM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . Interfaces of the CAPCOM Units . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17-25 [2] 17-27 [2] 17-29 [2] 17-34 [2] 17-36 [2] 17-37 [2] Capture/Compare Unit 6 (CAPCOM6) . . . . . . . . . . . . . . . . . . . . . . 18-1 [2] Timer T12 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 [2] Timer T12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 [2] T12 Compare Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2] Dead-Time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 [2] T12 Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24 [2] Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28 [2] Timer T13 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29 [2] T13 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32 [2] T13 Compare Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37 [2] Timer Block Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41 [2] Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47 [2] Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50 [2] Hall Pattern Compare Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51 [2] Sampling of the Hall Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-52 [2] Brushless DC-Motor Control with Timer T12 Block . . . . . . . . . . . 18-53 [2] Hall Mode Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-55 [2] Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 [2] Output Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-65 [2] Shadow Register Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . 18-69 [2] Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71 [2] Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80 [2] Interfaces of the CAPCOM6 Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-81 [2] Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . 19-1 [2] Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 [2] Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 [2] Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 [2] Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2] Transmit FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2] Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2] Receive FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2] FIFO Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 [2] IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 [2] RxD/TxD Data Path Selection in Asynchronous Modes . . . . . . . 19-17 [2] Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 [2] I-7 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 19.3.1 19.3.2 19.3.3 19.4 19.4.1 19.4.2 19.5 19.5.1 19.5.2 19.5.3 19.5.4 19.6 19.7 19.8 19.9 20 20.1 20.2 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.2.7 20.2.8 20.3 21 21.1 21.2 21.3 21.3.1 21.3.2 21.3.3 21.3.4 21.3.5 21.3.6 21.4 21.5 21.6 21.7 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baudrate in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . Baudrate in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . Autobaud Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Frames for Autobaud Detection . . . . . . . . . . . . . . . . . . . . . Baudrate Selection and Calculation . . . . . . . . . . . . . . . . . . . . . . . Overwriting Registers on Successful Autobaud Detection . . . . . Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces of the ASC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-20 [2] 19-20 [2] 19-20 [2] 19-22 [2] 19-22 [2] 19-26 [2] 19-27 [2] 19-27 [2] 19-28 [2] 19-29 [2] 19-33 [2] 19-34 [2] 19-35 [2] 19-39 [2] 19-56 [2] High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . 20-1 [2] Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2] Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2] Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 [2] Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 [2] Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 [2] Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2] Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2] Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2] SSC Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 [2] Port Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . 20-17 [2] Interfaces of the SSC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 [2] IIC-Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2] Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 [2] Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 [2] IIC-Bus Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2] Operation in Single-Master Mode . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2] Operation in Multimaster Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2] Operation in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2] Transmit/Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 [2] Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 [2] Notes for Programming the IIC-Bus Module . . . . . . . . . . . . . . . . 21-16 [2] Interrupt Request Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 [2] Port Connection and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 21-19 [2] Interfaces of the IIC-Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 [2] IIC-Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 [2] I-8 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 22 22.1 22.1.1 22.1.2 22.1.2.1 22.1.2.2 22.1.2.3 22.1.3 22.1.3.1 22.1.3.2 22.1.3.3 22.1.3.4 22.1.3.5 22.1.3.6 22.1.3.7 22.1.4 22.1.4.1 22.1.4.2 22.1.4.3 22.1.4.4 22.1.4.5 22.1.5 22.1.5.1 22.1.5.2 22.1.6 22.1.6.1 22.1.6.2 22.1.6.3 22.1.7 22.1.7.1 22.1.7.2 22.1.7.3 22.1.8 22.1.9 22.1.10 22.2 22.2.1 22.2.2 22.2.3 22.2.4 22.3 22.3.1 Page TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2] Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2] Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2] TwinCAN Control Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 [2] Initialization Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 [2] Interrupt Request Compressor . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2] Global Control and Status Logic . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2] CAN Node Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 [2] Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 [2] Timing Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 [2] Bitstream Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2] Error Handling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2] Node Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 [2] Message Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . 22-13 [2] Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 [2] Message Handling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 [2] Arbitration and Acceptance Mask Register . . . . . . . . . . . . . . . 22-16 [2] Handling of Remote and Data Frames . . . . . . . . . . . . . . . . . . 22-17 [2] Handling of Transmit Message Objects . . . . . . . . . . . . . . . . . . 22-18 [2] Handling of Receive Message Objects . . . . . . . . . . . . . . . . . . 22-21 [2] Single Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 [2] CAN Message Object Buffer (FIFO) . . . . . . . . . . . . . . . . . . . . . . 22-24 [2] Buffer Access by the CAN Controller . . . . . . . . . . . . . . . . . . . 22-26 [2] Buffer Access by the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27 [2] Gateway Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28 [2] Normal Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 [2] Normal Gateway with FIFO Buffering . . . . . . . . . . . . . . . . . . . 22-33 [2] Shared Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36 [2] Programming the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . 22-40 [2] Configuration of CAN Node A/B . . . . . . . . . . . . . . . . . . . . . . . 22-40 [2] Initialization of Message Objects . . . . . . . . . . . . . . . . . . . . . . . 22-40 [2] Controlling a Message Transfer . . . . . . . . . . . . . . . . . . . . . . . 22-41 [2] Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 [2] Single Transmission Try Functionality . . . . . . . . . . . . . . . . . . . . 22-45 [2] Module Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-46 [2] TwinCAN Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-47 [2] Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-47 [2] CAN Node A/B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-49 [2] CAN Message Object Registers . . . . . . . . . . . . . . . . . . . . . . . . . 22-64 [2] Global CAN Control/Status Registers . . . . . . . . . . . . . . . . . . . . . 22-80 [2] XC167 Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . 22-82 [2] Interfaces of the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . 22-82 [2] I-9 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents 22.3.2 22.3.2.1 22.3.2.2 22.3.2.3 22.3.3 23 23.1 23.2 TwinCAN Module Related External Registers . . . . . . . . . . . . . . . System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 22-83 [2] 22-84 [2] 22-85 [2] 22-90 [2] 22-91 [2] Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2] PD+BUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2] LXBUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 [2] Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 [1+2] User's Manual I-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14 The General Purpose Timer Units The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. Each block has alternate input/output functions and specific interrupts associated with it. Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer. These registers are listed in Section 14.1.6. * * * * fGPT/4 maximum resolution 3 independent timers/counters Timers/counters can be concatenated 4 operating modes: - Timer Mode - Gated Timer Mode - Counter Mode - Incremental Interface Mode Reload and Capture functionality Separate interrupt lines * * Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution is fGPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation with extended functionality. These registers are listed in Section 14.2.7. The core timer T6 may be concatenated with timers of the CAPCOM units (T0, T1, T7, and T8). The following list summarizes the features which are supported: * * * * fGPT/2 maximum resolution 2 independent timers/counters Timers/counters can be concatenated 3 operating modes: - Timer Mode - Gated Timer Mode - Counter Mode Extended capture/reload functions via 16-bit capture/reload register CAPREL Separate interrupt lines * * User's Manual GPT_X71, V2.0 14-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1 Timer Block GPT1 From a programmer's point of view, the GPT1 block is composed of a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded. D ata R egiste rs T2 T3 T4 C o ntrol R egisters T2C O N T3C O N T4C O N SYSC O N 3 Inte rru pt C ontrol T2IC T3IC T4IC P ort R egisters O D P3 D P3 P3 A LTSEL0P3 P5 P5D ID IS E E Tx TxC O N TxIC SYSCON3 G P T 1 Tim er G P T 1 Tim er G P T 1 Tim er S ystem C trl. x R egister x C ontrol R egister x In terrupt C trl. R e g. R e g. 3 (P er. M gm t.) ODP3 DP3 P3 A LTS E L0P 3 P5 P 5D ID IS P ort P ort P ort P ort P ort P ort 3 3 3 3 5 5 O pen D rain C ontrol R egister D irection C ontrol R egister D ata R e gister A lterna te O utput S elect R eg. D ata R e gister D igital Inp ut D isable R eg. m c_ g p t0 1 0 0 _ re g iste rs.vsd Figure 14-1 SFRs Associated with Timer Block GPT1 All three timers of block GPT1 (T2, T3, T4) can run in one of 4 basic modes: Timer Mode, Gated Timer Mode, Counter Mode, or Incremental Interface Mode. All timers can count up or down. Each timer of GPT1 is controlled by a separate control register TxCON. Each timer has an input pin TxIN (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (up/down) may be programmed via software or may be dynamically altered by a signal at the External Up/Down control input TxEUD (alternate pin function). An overflow/underflow of core timer T3 is indicated by the Output Toggle Latch T3OTL, whose state may be output on the associated pin T3OUT (alternate pin function). The auxiliary timers T2 and T4 may additionally be concatenated with the core timer T3 (through T3OTL) or may be used as capture or reload registers for the core timer T3. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer count registers T2, T3, or T4, located in the non-bitaddressable SFR space (see Section 14.1.6). When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment, decrement, reload, or capture operation, the CPU write operation has priority in order to guarantee correct results. User's Manual GPT_X71, V2.0 14-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT1 block. The input and output lines of GPT1 are connected to pins of ports P3 and P5. The control registers for the port functions are located in the respective port modules. Note: The timing requirements for external input signals can be found in Section 14.1.5, Section 14.3 summarizes the module interface signals, including pins. T3CON.BPS1 f GPT 2n: 1 Basic clock Interrupt Request (T2IRQ) Aux. Timer T2 T2IN T2EUD T2 Mode Control U/D Reload Capture Interrupt Request (T3IRQ) T3 Mode Control U/D T3EUD Capture Reload T4IN T4EUD T4 Mode Control U/D Toggle Latch Core Timer T3 T3OTL T3OUT T3IN Aux. Timer T4 Interrupt Request (T4IRQ) mc_gpt0101_bldiax1.vsd Figure 14-2 GPT1 Block Diagram (n = 2 ... 5) User's Manual GPT_X71, V2.0 14-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.1 GPT1 Core Timer T3 Control The current contents of the core timer T3 are reflected by its count register T3. This register can also be written to by the CPU, for example, to set the initial start value. The core timer T3 is configured and controlled via its bitaddressable control register T3CON. GPT12E_T3CON Timer 3 Control Register 15 14 13 T3 ED GE rwh 12 11 10 SFR (FF42H/A1H) 9 8 7 6 T3R rw 5 4 T3M rw Reset Value: 0000H 3 2 1 T3I rw 0 T3 T3 R CH DIR DIR rh rwh BPS1 rw T3 T3 T3 T3 OTL OE UDE UD rwh rw rw rw Field T3RDIR Bits 15 Type rh Description Timer T3 Rotation Direction Flag 0 Timer T3 counts up 1 Timer T3 counts down Timer T3 Count Direction Change Flag This bit is set each time the count direction of timer T3 changes. T3CHDIR must be cleared by SW. 0 No change of count direction was detected 1 A change of count direction was detected Timer T3 Edge Detection Flag The bit is set each time a count edge is detected. T3EDGE must be cleared by SW. 0 No count edge was detected 1 A count edge was detected GPT1 Block Prescaler Control Selects the basic clock for block GPT1 (see also Section 14.1.5) 00 fGPT/8 01 fGPT/4 10 fGPT/32 11 fGPT/16 Timer T3 Overflow Toggle Latch Toggles on each overflow/underflow of T3. Can be set or reset by software (see separate description) T3CHDIR 14 rwh T3EDGE 13 rwh BPS1 [12:11] rw T3OTL 10 rwh User's Manual GPT_X71, V2.0 14-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field T3OE Bits 9 Type rw Description Overflow/Underflow Output Enable 0 Alternate Output Function Disabled 1 State of T3 toggle latch is output on pin T3OUT Timer T3 External Up/Down Enable1) 0 Input T3EUD is disconnected 1 Direction influenced by input T3EUD Timer T3 Up/Down Control1) 0 Timer T3 counts up 1 Timer T3 counts down Timer T3 Run Bit 0 Timer T3 stops 1 Timer T3 runs Timer T3 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reserved. Do not use this combination. 101 Reserved. Do not use this combination. 110 Incremental Interface Mode (Rotation Detection Mode) 111 Incremental Interface Mode (Edge Detection Mode) Timer T3 Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-7 for Timer Mode and Gated Timer Mode Table 14-2 for Counter Mode Table 14-3 for Incremental Interface Mode T3UDE 8 rw T3UD 7 rw T3R 6 rw T3M [5:3] rw T3I [2:0] rw 1) See Table 14-1 for encoding of bits T3UD and T3UDE. User's Manual GPT_X71, V2.0 14-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer T3 Run Control The core timer T3 can be started or stopped by software through bit T3R (Timer T3 Run Bit). This bit is relevant in all operating modes of T3. Setting bit T3R will start the timer, clearing bit T3R stops the timer. In gated timer mode, the timer will only run if T3R = 1 and the gate is active (high or low, as programmed). Note: When bit T2RC or T4RC in timer control register T2CON or T4CON is set, bit T3R will also control (start and stop) the auxiliary timer(s) T2 and/or T4. Count Direction Control The count direction of the GPT1 timers (core timer and auxiliary timers) can be controlled either by software or by the external input pin TxEUD (Timer Tx External Up/Down Control Input). These options are selected by bits TxUD and TxUDE in the respective control register TxCON. When the up/down control is provided by software (bit TxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bit TxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction. However, bit TxUD can still be used to reverse the actual count direction, as shown in Table 14-1. The count direction can be changed regardless of whether or not the timer is running. Note: When pin TxEUD is used as external count direction control input, it must be configured as input (its corresponding direction control bit must be cleared). Table 14-1 Pin TxEUD X X 0 1 0 1 GPT1 Timer Count Direction Control Bit TxUDE 0 0 1 1 1 1 Bit TxUD 0 1 0 0 1 1 Count Direction Count Up Count Down Count Up Count Down Count Down Count Up Bit TxRDIR 0 1 0 1 1 0 User's Manual GPT_X71, V2.0 14-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer 3 Output Toggle Latch The overflow/underflow signal of timer T3 is connected to a block named `Toggle Latch', shown in the timer mode diagrams. Figure 14-3 illustrates the details of this block. An overflow or underflow of T3 will clock two latches: The first latch represents bit T3OTL in control register T3CON. The second latch is an internal latch toggled by T3OTL's output. Both latch outputs are connected to the input control blocks of the auxiliary timers T2 and T4. The output level of the shadow latch will match the output level of T3OTL, but is delayed by one clock cycle. When the T3OTL value changes, this will result in a temporarily different output level from T3OTL and the shadow latch, which can trigger the selected count event in T2 and/or T4. When software writes to T3OTL, both latches are set or cleared simultaneously. In this case, both signals to the auxiliary timers carry the same level and no edge will be detected. Bit T3OE (overflow/underflow output enable) in register T3CON enables the state of T3OTL to be monitored via an external pin T3OUT. When T3OTL is linked to an external port pin (must be configured as output), T3OUT can be used to control external HW. If T3OE = 1, pin T3OUT outputs the state of T3OTL. If T3OE = 0, pin T3OUT outputs a high level (as long as the T3OUT alternate function is selected for the port pin). The trigger signals can serve as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4. As can be seen from Figure 14-3, when latch T3OTL is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. Therefore, no trigger condition is detected by T2/T4 in this case. S et/C lear (S W ) TxO E MUX 1 O verflow / U nd erflow 1 TxO TL Shadow Latch 0 T xO U T T o P ort Logic C ore Tim er T o g g le L a tch L o g ic T o A ux. Tim er Input Logic m c_ g p t0 1 0 6 _ o tl.vsd Figure 14-3 Block Diagram of the Toggle Latch Logic of Core Timer T3 User's Manual GPT_X71, V2.0 14-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.2 GPT1 Core Timer T3 Operating Modes Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 000B. In timer mode, T3 is clocked with the module's input clock fGPT divided by two programmable prescalers controlled by bitfields BPS1 and T3I in register T3CON. Please see Section 14.1.5 for details on the input clock options. T3IRQ fGPT Prescaler fT3 Count Core Timer T3 Toggle Latch T3OUT to T2/T4 BPS1 T3I T3R T3UD 0 =1 T3EUD T3UDE MCB05391 MUX 1 Up/Down Figure 14-4 Block Diagram of Core Timer T3 in Timer Mode User's Manual GPT_X71, V2.0 14-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 010B or 011B. Bit T3M.0 (T3CON.3) selects the active level of the gate input. The same options for the input frequency are available in gated timer mode as in timer mode (see Section 14.1.5). However, the input clock to the timer in this mode is gated by the external input pin T3IN (Timer T3 External Input). To enable this operation, the associated pin T3IN must be configured as input, that is, the corresponding direction control bit must contain 0. T3IRQ fGPT Prescaler Gate Ctrl. fT3 Count Core Timer T3 Toggle Latch T3OUT to T2/T4 BPS1 T3IN T3I T3R T3UD 0 =1 T3EUD T3UDE MCB05392 MUX 1 Up/Down Figure 14-5 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M = 010B, the timer is enabled when T3IN shows a low level. A high level at this line stops the timer. If T3M = 011B, line T3IN must have a high level in order to enable the timer. Additionally, the timer can be turned on or off by software using bit T3R. The timer will only run if T3R is 1 and the gate is active. It will stop if either T3R is 0 or the gate is inactive. Note: A transition of the gate signal at pin T3IN does not cause an interrupt request. User's Manual GPT_X71, V2.0 14-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Counter Mode Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 001B. In counter mode, timer T3 is clocked by a transition at the external input pin T3IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bitfield T3I in control register T3CON selects the triggering transition (see Table 14-2). T3IRQ Edge T3IN Select Count Core Timer T3 Toggle Latch T3OUT to T2/T4 T3I T3UD T3R 0 =1 T3EUD 1 MUX Up/Down T3UDE MCB05393 Figure 14-6 Block Diagram of Core Timer T3 in Counter Mode Table 14-2 T3I 000 001 010 011 1XX GPT1 Core Timer T3 (Counter Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter T3 is disabled Positive transition (rising edge) on T3IN Negative transition (falling edge) on T3IN Any transition (rising or falling edge) on T3IN Reserved. Do not use this combination For counter mode operation, pin T3IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T3IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5. User's Manual GPT_X71, V2.0 14-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Incremental Interface Mode Incremental interface mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 110B or 111B. In incremental interface mode, the two inputs associated with core timer T3 (T3IN, T3EUD) are used to interface to an incremental encoder. T3 is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input. T3IN Edge Count Core Timer T3 Toggle Latch T3OUT to T2/T4 Select T3I T3R T3 EDGE T3 RDIR _ >1 T3IRQ T3UD 0 =1 T3EUD Phase Detect T3UDE 1 MUX Change Detect T3M T3CH DIR T3M MCB05394 Figure 14-7 Block Diagram of Core Timer T3 in Incremental Interface Mode Bitfield T3I in control register T3CON selects the triggering transitions (see Table 14-3). The sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. So T3 is modified automatically according to the speed and the direction of the incremental encoder and, therefore, its contents always represent the encoder's current position. The interrupt request (T3IRQ) generation mode can be selected: In Rotation Detection Mode (T3M = 110B), an interrupt request is generated each time the count direction of T3 changes. In Edge Detection Mode (T3M = 111B), an interrupt request is generated each time a count edge for T3 is detected. Count direction, changes in the count direction, and count requests are monitored by status bits T3RDIR, T3CHDIR, and T3EDGE in register T3CON. User's Manual GPT_X71, V2.0 14-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Table 14-3 T3I 000 001 010 011 1XX Core Timer T3 (Incremental Interface Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter T3 stops. Any transition (rising or falling edge) on T3IN. Any transition (rising or falling edge) on T3EUD. Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD). Reserved. Do not use this combination. The incremental encoder can be connected directly to the XC167 without external interface logic. In a standard system, however, comparators will be employed to convert the encoder's differential outputs (such as A, A) to digital signals (such as A). This greatly increases noise immunity. Note: The third encoder output T0, which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a reset of timer T3 (for example via PEC transfer from ZEROS). Signal Conditioning A A B B T0 T0 A Encoder Controller T3Input B T3Input T0 Interrupt MCS04372 Figure 14-8 Connection of the Encoder to the XC167 For incremental interface operation, the following conditions must be met: * * * Bitfield T3M must be 110B or 111B. Both pins T3IN and T3EUD must be configured as input, i.e. the respective direction control bits must be 0. Bit T3UDE must be 1 to enable automatic external direction control. The maximum count frequency allowed in incremental interface mode depends on the selected prescaler value. To ensure that a transition of any input signal is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5. User's Manual GPT_X71, V2.0 14-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units As in incremental interface mode two input signals with a 90 phase shift are evaluated, their maximum input frequency can be half the maximum count frequency. In incremental interface mode, the count direction is automatically derived from the sequence in which the input signals change, which corresponds to the rotation direction of the connected sensor. Table 14-4 summarizes the possible combinations. Table 14-4 GPT1 Core Timer T3 (Incremental Interface Mode) Count Direction T3IN Input Falling Up Down Rising Up Down T3EUD Input Falling Down Up Level on Respective other Input Rising High Low Down Up Figure 14-9 and Figure 14-10 give examples of T3's operation, visualizing count signal generation and direction control. They also show how input jitter is compensated, which might occur if the sensor rests near to one of its switching points. Forward T3IN T3EUD Jitter Backward Jitter Forward Contents of T3 Up Down Up Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input, i.e. T3I = '011 B'. MCT04373 Figure 14-9 Evaluation of Incremental Encoder Signals, 2 Count Inputs User's Manual GPT_X71, V2.0 14-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Forward T3IN T3EUD Jitter Backward Jitter Forward Contents of T3 Up Down Up Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input T3IN, i.e. T3I = '001 B'. MCT04374 Figure 14-10 Evaluation of Incremental Encoder Signals, 1 Count Input Note: Timer T3 operating in incremental interface mode automatically provides information on the sensor's current position. Dynamic information (speed, acceleration, deceleration) may be obtained by measuring the incoming signal periods. This is facilitated by an additional special capture mode for timer T5 (see Section 14.2.5). User's Manual GPT_X71, V2.0 14-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.3 GPT1 Auxiliary Timers T2/T4 Control Auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer mode, gated timer mode, counter mode, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3. In addition to these 4 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. The start/stop function of the auxiliary timers can be remotely controlled by the T3 run control bit. Several timers may thus be controlled synchronously. The current contents of an auxiliary timer are reflected by its count register T2 or T4, respectively. These registers can also be written to by the CPU, for example, to set the initial start value. The individual configurations for timers T2 and T4 are determined by their bitaddressable control registers T2CON and T4CON, which are organized identically. Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers. Note: The auxiliary timers have no output toggle latch and no alternate output function. GPT12E_T2CON Timer 2 Control Register 15 14 13 T2 ED GE rwh 12 T2 IR DIS rw 11 10 - SFR (FF40H/A0H) 9 8 7 6 T2R rw 5 4 T2M rw Reset Value: 0000H 3 2 1 T2I rw 0 T2 T2 R CH DIR DIR rh rwh T2 T2 T2 RC UDE UD rw rw rw GPT12E_T4CON Timer 4 Control Register 15 14 13 T4 ED GE rwh 12 T4 IR DIS rw 11 10 - SFR (FF44H/A2H) 9 8 7 6 T4R rw 5 4 T4M rw Reset Value: 0000H 3 2 1 T4I rw 0 T4 T4 R CH DIR DIR rh rwh T4 T4 T4 RC UDE UD rw rw rw Field TxRDIR Bits 15 Type rh Description Timer Tx Rotation Direction 0 Timer x counts up 1 Timer x counts down User's Manual GPT_X71, V2.0 14-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field TxCHDIR Bits 14 Type rwh Description Timer Tx Count Direction Change This bit is set each time the count direction of timer Tx changes. TxCHDIR must be cleared by SW. 0 No change in count direction was detected 1 A change in count direction was detected Timer Tx Edge Detection The bit is set each time a count edge is detected. TxEDGE must be cleared by SW. 0 No count edge was detected 1 A count edge was detected Timer Tx Interrupt Request Disable 0 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is enabled 1 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is disabled Timer Tx Remote Control 0 Timer Tx is controlled by its own run bit TxR 1 Timer Tx is controlled by the run bit T3R of core timer 3, not by bit TxR Timer Tx External Up/Down Enable1) 0 Input TxEUD is disconnected 1 Direction influenced by input TxEUD Timer Tx Up/Down Control1) 0 Timer Tx counts up 1 Timer Tx counts down Timer Tx Run Bit 0 Timer Tx stops 1 Timer Tx runs Note: This bit only controls timer Tx if bit TxRC = 0. TxEDGE 13 rwh TxIRDIS 12 rw TxRC 9 rw TxUDE 8 rw TxUD 7 rw TxR 6 rw User's Manual GPT_X71, V2.0 14-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field TxM Bits [5:3] Type rw Description Timer Tx Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode (Rotation Detect.) 111 Incremental Interface Mode (Edge Detection) Timer Tx Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-7 for Timer Mode and Gated Timer Mode Table 14-2 for Counter Mode Table 14-3 for Incremental Interface Mode TxI [2:0] rw 1) See Table 14-1 for encoding of bits TxUD and TxUDE. Timer T2/T4 Run Control Each of the auxiliary timers T2 and T4 can be started or stopped by software in two different ways: * * Through the associated timer run bit (T2R or T4R). In this case it is required that the respective control bit TxRC = 0. Through the core timer's run bit (T3R). In this case the respective remote control bit must be set (TxRC = 1). The selected run bit is relevant in all operating modes of T2/T4. Setting the bit will start the timer, clearing the bit stops the timer. In gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). Note: If remote control is selected T3R will start/stop timer T3 and the selected auxiliary timer(s) synchronously. Count Direction Control The count direction of the GPT1 timers (core timer and auxiliary timers) is controlled in the same way, either by software or by the external input pin TxEUD. Please refer to the description in Table 14-1. Note: When pin TxEUD is used as external count direction control input, it must be configured as input (its corresponding direction control bit must be cleared). User's Manual GPT_X71, V2.0 14-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes The operation of the auxiliary timers in the basic operating modes is almost identical with the core timer's operation, with very few exceptions. Additionally, some combined operating modes can be selected. Timers T2 and T4 in Timer Mode Timer mode for an auxiliary timer Tx is selected by setting its bitfield TxM in register TxCON to 000B. fTx Count Auxiliary Timer Tx fGPT Prescaler TxIRQ BPS1 TxI TxR T3R 0 1 MUX TxRC TxUD 0 =1 TxEUD TxUDE x = 2, 4 MCB05395 MUX 1 Up/Down Figure 14-11 Block Diagram of an Auxiliary Timer in Timer Mode User's Manual GPT_X71, V2.0 14-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timers T2 and T4 in Gated Timer Mode Gated timer mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 010B or 011B. Bit TxM.0 (TxCON.3) selects the active level of the gate input. Note: A transition of the gate signal at line TxIN does not cause an interrupt request. fGPT Prescaler Gate Ctrl. fTx Count Auxiliary Timer Tx TxIRQ BPS1 TxIN TxI TxM TxR T3R 0 1 MUX TxRC TxUD 0 =1 TxEUD TxUDE x = 2, 4 MCB05396 MUX 1 Up/Down Figure 14-12 Block Diagram of an Auxiliary Timer in Gated Timer Mode Note: There is no output toggle latch for T2 and T4. Start/stop of an auxiliary timer can be controlled locally or remotely. User's Manual GPT_X71, V2.0 14-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timers T2 and T4 in Counter Mode Counter mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 001B. In counter mode, an auxiliary timer can be clocked either by a transition at its external input line TxIN, or by a transition of timer T3's toggle latch T3OTL. The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. Bitfield TxI in control register TxCON selects the triggering transition (see Table 14-5). TxIN T3 Toggle Latch 0 1 Select MUX Edge Count Auxiliary Timer Tx TxIRQ TxI.2 TxR T3R TxI 0 1 MUX TxRC TxUD 0 =1 TxEUD TxUDE x = 2, 4 MCB05397 MUX 1 Up/Down Figure 14-13 Block Diagram of an Auxiliary Timer in Counter Mode Table 14-5 T2I/T4I X00 001 010 011 101 110 111 GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter Tx is disabled Positive transition (rising edge) on TxIN Negative transition (falling edge) on TxIN Any transition (rising or falling edge) on TxIN Positive transition (rising edge) of T3 toggle latch T3OTL Negative transition (falling edge) of T3 toggle latch T3OTL Any transition (rising or falling edge) of T3 toggle latch T3OTL Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. User's Manual GPT_X71, V2.0 14-20 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units For counter operation, pin TxIN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5. Timers T2 and T4 in Incremental Interface Mode Incremental interface mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 110B or 111B. In incremental interface mode, the two inputs associated with an auxiliary timer Tx (TxIN, TxEUD) are used to interface to an incremental encoder. Tx is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input. Overflow Underflow TxIN Edge Count Auxiliary Timer Tx Select TxI TxR T3R 0 1 MUX Tx Edge Tx RDIR TxRC TxUD 0 =1 TxEUD Phase Detect TxUDE 1 MUX & _ >1 TxIRQ Change Detect TxM & TxCH DIR TxM TxIRDIS MCB05398 Figure 14-14 Block Diagram of an Auxiliary Timer in Incremental Interface Mode The operation of the auxiliary timers T2 and T4 in incremental interface mode and the interrupt generation are the same as described for the core timer T3. The descriptions, figures and tables apply accordingly. User's Manual GPT_X71, V2.0 14-21 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T3OTL is selected to clock the auxiliary timer. * 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T3. Thus, the two timers form a 32-bit timer. 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer + T3OTL + 16-bit auxiliary timer). As long as bit T3OTL is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. * The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T3, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. T3IRQ fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 TxI Up/Down TxIN 0 1 MUX Edge Count Select Auxiliary Timer Tx TxIRQ TxI.2 TxI TxR T3R 0 1 MUX Up/Down TxRC x = 2, 4 MCA05399 Figure 14-15 Concatenation of Core Timer T3 and an Auxiliary Timer User's Manual GPT_X71, V2.0 14-22 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Auxiliary Timer in Reload Mode Reload Mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 100B. In reload mode, the core timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals. The trigger signal is selected the same way as the clock source for counter mode (see Table 14-5), i.e. a transition of the auxiliary timer's input TxIN or the toggle latch T3OTL may trigger the reload. Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independently of its run flag T2R or T4R. The timer input pin TxIN must be configured as input if it shall trigger a reload operation. T3IRQ fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 TxI Up/Down TxIN 0 1 MUX Edge Reload TxIRQ Select TxI.2 TxI Auxiliary Timer Tx x = 2, 4 MCA05400 Figure 14-16 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal, T3 is loaded with the contents of the respective timer register (T2 or T4) and the respective interrupt request flag (T2IR or T4IR) is set. Note: When a T3OTL transition is selected for the trigger signal, the interrupt request flag T3IR will also be set upon a trigger, indicating T3's overflow or underflow. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. To ensure that a transition of the reload input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.1.5. The reload mode triggered by the T3 toggle latch can be used in a number of different configurations. The following functions can be performed, depending on the selected active transition: User's Manual GPT_X71, V2.0 14-23 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units * If both a positive and a negative transition of T3OTL are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. This is the standard reload mode (reload on overflow/underflow). If either a positive or a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow. Using this "single-transition" mode for both auxiliary timers allows to perform very flexible Pulse Width Modulation (PWM). One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL, the other is programmed for a reload on a negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers. * * Figure 14-17 shows an example for the generation of a PWM signal using the "singletransition" reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions). The PWM signal can be output on pin T3OUT if T3OE = 1. With this method, the high and low time of the PWM signal can be varied in a wide range. Note: The output toggle latch T3OTL is accessible via software and may be changed, if required, to modify the PWM signal. However, this will NOT trigger the reloading of T3. User's Manual GPT_X71, V2.0 14-24 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Auxiliary Timer T2 0 1 Select Edge T2IN MUX Reload T2IRQ T2I.2 T2I T3IRQ fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 T3I Up/Down T4IN 0 1 MUX Edge Reload T4IRQ Select T4I.2 T4I Auxiliary Timer T4 MCA05401 Figure 14-17 GPT1 Timer Reload Configuration for PWM Generation Note: Although possible, selecting the same reload trigger event for both auxiliary timers should be avoided. In such a case, both reload registers would try to load the core timer at the same time. If this combination is selected, T2 is disregarded and the contents of T4 is reloaded. User's Manual GPT_X71, V2.0 14-25 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Auxiliary Timer in Capture Mode Capture mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 101B. In capture mode, the contents of the core timer T3 are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer's external input pin TxIN. The capture trigger signal can be a positive, a negative, or both a positive and a negative transition. The two least significant bits of bitfield TxI select the active transition (see Table 14-5). Bit 2 of TxI is irrelevant for capture mode and must be cleared (TxI.2 = 0). Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4) stops independently of its run flag T2R or T4R. T3IRQ fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 T3I Up/Down to Ty Edge TxIN Select Capture TxIRQ TxI Auxiliary Timer Tx x = 2, 4 y = 4, 2 MCA05402 Figure 14-18 GPT1 Auxiliary Timer in Capture Mode Upon a trigger (selected transition) at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set. For capture mode operation, the respective timer input pin TxIN must be configured as input. To ensure that a transition of the capture input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.1.5. User's Manual GPT_X71, V2.0 14-26 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.5 GPT1 Clock Signal Control All actions within the timer block GPT1 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield BPS1 in register T3CON (see Figure 14-2). The count clock can be generated in two different ways: * * Internal count clock, derived from GPT1's basic clock via a programmable prescaler, is used for (gated) timer mode. External count clock, derived from the timer's input pin(s), is used for counter mode. For both ways, the basic clock determines the maximum count frequency and the timer's resolution: Table 14-6 Basic Clock Selection for Block GPT1 BPS1 = 01B F(BPS1) =4 BPS1 = 00B2) BPS1 = 11B F(BPS1) =8 F(BPS1) = 16 BPS1 = 10B F(BPS1) = 32 Block Prescaler1) Prescaling Factor for GPT1: F(BPS1) Maximum External Count Frequency Input Signal Stable Time 2) Default after reset. fGPT/8 4 x tGPT fGPT/16 8 x tGPT fGPT/32 16 x tGPT fGPT/64 32 x tGPT 1) Please note the non-linear encoding of bitfield BPS1. Internal Count Clock Generation In timer mode and gated timer mode, the count clock for each GPT1 timer is derived from the GPT1 basic clock by a programmable prescaler, controlled by bitfield TxI in the respective timer's control register TxCON. The count frequency fTx for a timer Tx and its resolution rTx are scaled linearly with lower clock frequencies, as can be seen from the following formula: f Tx = ------------------------------------------- F ( BPS1 ) x 2 f GPT -------------------------------------------r Tx [ s ] = F ( BPS1 ) x 2 f GPT [ MHz ] (14.1) The effective count frequency depends on the common module clock prescaler factor F(BPS1) as well as on the individual input prescaler factor 2 User's Manual GPT_X71, V2.0 14-27 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Table 14-7 GPT1 Overall Prescaler Factors for Internal Count Clock Common Prescaler for Module Clock1) BPS1 = 01B 4 8 16 32 64 128 256 512 BPS1 = 00B 8 16 32 64 128 256 512 1024 BPS1 = 11B 16 32 64 128 256 512 1024 2048 BPS1 = 10B 32 64 128 256 512 1024 2048 4096 Individual Prescaler for Tx TxI = 000B TxI = 001B TxI = 010B TxI = 011B TxI = 100B TxI = 101B TxI = 110B TxI = 111B 1) Please note the non-linear encoding of bitfield BPS1. Table 14-8 Frequency 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.06 kHz 19.53 kHz 9.77 kHz 4.88 kHz 2.44 kHz GPT1 Timer Parameters Resolution Period 400 ns 800 ns 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s 409.6 s Overall Divider Factor System Clock = 40 MHz Frequency Resolution Period 10.0 MHz 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.55 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1.678 s 3.355 s 6.711 s System Clock = 10 MHz 26.21 ms 4 52.43 ms 8 104.9 ms 16 209.7 ms 32 419.4 ms 64 838.9 ms 128 1.678 s 3.355 s 6.711 s 13.42 s 26.84 s 256 512 1024 2048 4096 156.25 kHz 6.4 s 78.125 kHz 12.8 s 39.06 kHz 19.53 kHz 9.77 kHz 25.6 s 51.2 s 102.4 s User's Manual GPT_X71, V2.0 14-28 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units External Count Clock Input The external input signals of the GPT1 block are sampled with the GPT1 basic clock (see Figure 14-2). To ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. A signal transition is recognized if two subsequent samples of the input signal represent different levels. Therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than half the basic clock. Table 14-9 summarizes the resulting requirements for external GPT1 input signals. Table 14-9 GPT1 External Input Signal Limits System Clock = 40 MHz GPT1 Input Divider Phase Max. Input Min. Level BPS1 Duration Frequency Hold Time 01B 00B 11B 10B 4 x tGPT 8 x tGPT 16 x tGPT 32 x tGPT 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 100 ns 200 ns 400 ns 800 ns System Clock = 10 MHz Input Max. Input Min. Level Frequ. Frequency Hold Time Factor 1.25 MHz 625.0 kHz 312.5 kHz 156.25 kHz 400 ns 800 ns 1.6 s 3.2 s fGPT/8 fGPT/16 fGPT/32 fGPT/64 These limitations are valid for all external input signals to GPT1, including the external count signals in counter mode and incremental interface mode, the gate input signals in gated timer mode, and the external direction signals. 14.1.6 GPT1 Timer Registers GPT12E_Tx Timer x Count Register 15 14 13 12 11 10 SFR (FE4xH/2yH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 Txvalue rwh Table 14-10 GPT1 Timer Register Locations Timer Register T3 T2 T4 User's Manual GPT_X71, V2.0 Physical Address FE42H FE40H FE44H 14-29 8-Bit Address 21H 20H 22H V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.7 Interrupt Control for GPT1 Timers When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000H to FFFFH (when counting down), its interrupt request flag (T2IR, T3IR or T4IR) in register TxIC will be set. This will cause an interrupt to the respective timer interrupt vector (T2INT, T3INT or T4INT) or trigger a PEC service, if the respective interrupt enable bit (T2IE, T3IE or T4IE in register TxIC) is set. There is an interrupt control register for each of the three timers. GPT12E_T2IC Timer 2 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF60H/B0H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T2IR T2IE rw rwh rw ILVL rw GLVL rw GPT12E_T3IC Timer 3 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF62H/B1H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T3IR T3IE rw rwh rw ILVL rw GLVL rw GPT12E_T4IC Timer 4 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF64H/B2H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T4IR T4IE rw rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual GPT_X71, V2.0 14-30 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2 Timer Block GPT2 From a programmer's point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded. Data Registers T5 T6 CAPREL SYSCON3 Control Registers T5CON T6CON Interrupt Control T5IC T6IC CRIC Port Registers ODP3 DP3 P3 ALTSEL0P3 P5 P5DIDIS E E Tx CAPREL TxCON TxIC SYSCON3 GPT2 Timer x Register GPT2 Capture/Reload Register GPT2 Timer x Control Register GPT2 Timer x Interrupt Ctrl. Reg. System Ctrl. Reg. 3 (Per. Mgmt.) ODP3 DP3 P3 ALTSEL0P3 P5 P5DIDIS Port 3 Open Drain Control Register Port 3 Direction Control Register Port 3 Data Register Port 3 Alternate Output Select Reg. Port 5 Data Register Port 5 Digital Input Disable Reg. mc_gpt0107_registers.vsd Figure 14-19 SFRs Associated with Timer Block GPT2 Both timers of block GPT2 (T5, T6) can run in one of 3 basic modes: Timer Mode, Gated Timer Mode, or Counter Mode. All timers can count up or down. Each timer of GPT2 is controlled by a separate control register TxCON. Each timer has an input pin TxIN (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (up/down) may be programmed via software or may be dynamically altered by a signal at the External Up/Down control input TxEUD (alternate pin function). An overflow/underflow of core timer T6 is indicated by the Output Toggle Latch T6OTL, whose state may be output on the associated pin T6OUT (alternate pin function). The auxiliary timer T5 may additionally be concatenated with core timer T6 (through T6OTL). The Capture/Reload register CAPREL can be used to capture the contents of timer T5, or to reload timer T6. A special mode facilitates the use of register CAPREL for both functions at the same time. This mode allows frequency multiplication. The capture function is triggered by the input pin CAPIN, or by GPT1 timer's T3 input lines T3IN and T3EUD. The reload function is triggered by an overflow or underflow of timer T6. Overflows/underflows of timer T6 may also clock the timers of the CAPCOM units. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer count registers T5 or T6, located in the non-bitaddressable SFR User's Manual GPT_X71, V2.0 14-31 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units space (see Section 14.2.7). When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment, decrement, reload, or capture operation, the CPU write operation has priority in order to guarantee correct results. The interrupts of GPT2 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT2 block. The input and output lines of GPT2 are connected to pins of Ports P3 and P5. The control registers for the port functions are located in the respective port modules. Note: The timing requirements for external input signals can be found in Section 14.2.6, Section 14.3 summarizes the module interface signals, including pins. T6CON.BPS2 f GPT 2n: 1 Basic clock GPT2 Timer T5 T5IN T5EUD T5 Mode Control U/D Clear Interrupt Request (T5IR) Capture CAPIN T3IN/ T3EUD CAPREL Mode Control GPT2 CAPREL Interrupt Request (CRIR) Interrupt Request (T6IR) Toggle FF Reload Clear GPT2 Timer T6 T6 Mode Control U/D T6OTL T6OUT T6IN T6EUD T6OUF mc_gpt0108_bldiax4.vsd Figure 14-20 GPT2 Block Diagram User's Manual GPT_X71, V2.0 14-32 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.1 GPT2 Core Timer T6 Control The current contents of the core timer T6 are reflected by its count register T6. This register can also be written to by the CPU, for example, to set the initial start value. The core timer T6 is configured and controlled via its bitaddressable control register T6CON. GPT12E_T6CON Timer 6 Control Register 15 14 13 12 11 10 SFR (FF48H/A4H) 9 8 7 6 T6R rw 5 4 T6M rw Reset Value: 0000H 3 2 1 T6I rw 0 T6 T6 SR CLR rw rw BPS2 rw T6 T6 T6 T6 OTL OE UDE UD rwh rw rw rw Field T6SR Bits 15 Type rw Description Timer 6 Reload Mode Enable 0 Reload from register CAPREL Disabled 1 Reload from register CAPREL Enabled Timer T6 Clear Enable Bit 0 Timer T6 is not cleared on a capture event 1 Timer T6 is cleared on a capture event GPT2 Block Prescaler Control Selects the basic clock for block GPT2 (see also Section 14.2.6) 00 fGPT/4 01 fGPT/2 10 fGPT/16 11 fGPT/8 Timer T6 Overflow Toggle Latch Toggles on each overflow/underflow of T6. Can be set or reset by software (see separate description) Overflow/Underflow Output Enable 0 Alternate Output Function Disabled 1 State of T6 toggle latch is output on pin T6OUT Timer T6 External Up/Down Enable1) 0 Input T6EUD is disconnected 1 Direction influenced by input T6EUD T6CLR 14 rw BPS2 [12:11] rw T6OTL 10 rwh T6OE 9 rw T6UDE 8 rw User's Manual GPT_X71, V2.0 14-33 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field T6UD Bits 7 Type rw Description Timer T6 Up/Down Control1) 0 Timer T6 counts up 1 Timer T6 counts down Timer T6 Run Bit 0 Timer T6 stops 1 Timer T6 runs Timer T6 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reserved. Do not use this combination. 101 Reserved. Do not use this combination. 110 Reserved. Do not use this combination. 111 Reserved. Do not use this combination. Timer T6 Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-16 for Timer Mode and Gated Timer Mode Table 14-12 for Counter Mode T6R 6 rw T6M [5:3] rw T6I [2:0] rw 1) See Table 14-11 for encoding of bits T6UD and T6UDE. User's Manual GPT_X71, V2.0 14-34 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer T6 Run Control The core timer T6 can be started or stopped by software through bit T6R (timer T6 run bit). This bit is relevant in all operating modes of T6. Setting bit T6R will start the timer, clearing bit T6R stops the timer. In gated timer mode, the timer will only run if T6R = 1 and the gate is active (high or low, as programmed). Note: When bit T5RC in timer control register T5CON is set, bit T6R will also control (start and stop) the Auxiliary Timer T5. Count Direction Control The count direction of the GPT2 timers (core timer and auxiliary timer) can be controlled either by software or by the external input pin TxEUD (Timer Tx External Up/Down Control Input). These options are selected by bits TxUD and TxUDE in the respective control register TxCON. When the up/down control is provided by software (bit TxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bit TxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction. However, bit TxUD can still be used to reverse the actual count direction, as shown in Table 14-11. The count direction can be changed regardless of whether or not the timer is running. Table 14-11 GPT2 Timer Count Direction Control Pin TxEUD X X 0 1 0 1 Bit TxUDE 0 0 1 1 1 1 Bit TxUD 0 1 0 0 1 1 Count Direction Count Up Count Down Count Up Count Down Count Down Count Up User's Manual GPT_X71, V2.0 14-35 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer 6 Output Toggle Latch The overflow/underflow signal of timer T6 is connected to a block named `Toggle Latch', shown in the timer mode diagrams. Figure 14-21 illustrates the details of this block. An overflow or underflow of T6 will clock two latches: The first latch represents bit T6OTL in control register T6CON. The second latch is an internal latch toggled by T6OTL's output. Both latch outputs are connected to the input control block of the auxiliary timer T5. The output level of the shadow latch will match the output level of T6OTL, but is delayed by one clock cycle. When the T6OTL value changes, this will result in a temporarily different output level from T6OTL and the shadow latch, which can trigger the selected count event in T5. When software writes to T6OTL, both latches are set or cleared simultaneously. In this case, both signals to the auxiliary timers carry the same level and no edge will be detected. Bit T6OE (overflow/underflow output enable) in register T6CON enables the state of T6OTL to be monitored via an external pin T6OUT. When T6OTL is linked to an external port pin (must be configured as output), T6OUT can be used to control external HW. If T6OE = 1, pin T6OUT outputs the state of T6OTL. If T6OE = 0, pin T6OUT outputs a high level (while it selects the timer output signal). As can be seen from Figure 14-21, when latch T6OTL is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. Therefore, no trigger condition is detected by T5 in this case. S et/C lear (S W ) TxO E MUX 1 O verflow / U nd erflow 1 TxO TL Shadow Latch 0 T xO U T T o P ort Logic C ore Tim er T o g g le L a tch L o g ic T o A ux. Tim er Input Logic m c_ g p t0 1 0 6 _ o tl.vsd Figure 14-21 Block Diagram of the Toggle Latch Logic of Core Timer T6 Note: T6 is also used to clock the timers in the CAPCOM units. For this purpose, there is a direct internal connection between the T6 overflow/underflow line and the CAPCOM timers (signal T6OUF). User's Manual GPT_X71, V2.0 14-36 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.2 GPT2 Core Timer T6 Operating Modes Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 000B. In this mode, T6 is clocked with the module's input clock fGPT divided by two programmable prescalers controlled by bitfields BPS2 and T6I in register T6CON. Please see Section 14.2.6 for details on the input clock options. T6IRQ fGPT Prescaler fT6 Count Core Timer T6 Toggle Latch T6OUT to T5/ BPS2 T6I T6R CAPREL T6UD 0 =1 T6EUD T6UDE 1 MUX T6OUF Up/Down MCB05403_X4 Figure 14-22 Block Diagram of Core Timer T6 in Timer Mode User's Manual GPT_X71, V2.0 14-37 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Gated Timer Mode Gated timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 010B or 011B. Bit T6M.0 (T6CON.3) selects the active level of the gate input. The same options for the input frequency are available in gated timer mode as in timer mode (see Section 14.2.6). However, the input clock to the timer in this mode is gated by the external input pin T6IN (Timer T6 External Input). To enable this operation, the associated pin T6IN must be configured as input (the corresponding direction control bit must contain 0). T6IRQ fGPT Prescaler Gate Ctrl. fT6 Count Core Timer T6 Toggle Latch T6OUT to T5, BPS2 T6IN T6I T6R Clear CAPREL T6UD 0 =1 T6EUD T6UDE 1 MUX T6OUF Up/Down MCB05404_X4 Figure 14-23 Block Diagram of Core Timer T6 in Gated Timer Mode If T6M = 010B, the timer is enabled when T6IN shows a low level. A high level at this line stops the timer. If T6M = 011B, line T6IN must have a high level in order to enable the timer. Additionally, the timer can be turned on or off by software using bit T6R. The timer will only run if T6R is 1 and the gate is active. It will stop if either T6R is 0 or the gate is inactive. Note: A transition of the gate signal at pin T6IN does not cause an interrupt request. User's Manual GPT_X71, V2.0 14-38 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Counter Mode Counter mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 001B. In counter mode, timer T6 is clocked by a transition at the external input pin T6IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bitfield T6I in control register T6CON selects the triggering transition (see Table 14-12). T6IRQ Edge T6IN Select Count Core Timer T6 Toggle Latch T6OUT to T5, T6I T6UD T6R Clear CAPREL T6OUF 0 =1 1 MUX Up/Down T6EUD T6UDE MCB05405_X4 Figure 14-24 Block Diagram of Core Timer T6 in Counter Mode Table 14-12 GPT2 Core Timer T6 (Counter Mode) Input Edge Selection T6I 000 001 010 011 1XX Triggering Edge for Counter Increment/Decrement None. Counter T6 is disabled Positive transition (rising edge) on T6IN Negative transition (falling edge) on T6IN Any transition (rising or falling edge) on T6IN Reserved. Do not use this combination For counter mode operation, pin T6IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T6IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.2.6. User's Manual GPT_X71, V2.0 14-39 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.3 GPT2 Auxiliary Timer T5 Control Auxiliary timer T5 can be configured for timer mode, gated timer mode, or counter mode with the same options for the timer frequencies and the count signal as the core timer T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The contents of T5 may be captured to register CAPREL upon an external or an internal trigger. The start/stop function of the auxiliary timers can be remotely controlled by the T6 run control bit. Several timers may thus be controlled synchronously. The current contents of the auxiliary timer are reflected by its count register T5. This register can also be written to by the CPU, for example, to set the initial start value. The individual configurations for timer T5 are determined by its bitaddressable control register T5CON. Some bits in this register also control the function of the CAPREL register. Note that functions which are present in all timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers. Note: The auxiliary timer has no output toggle latch and no alternate output function. GPT12E_T5CON Timer 5 Control Register 15 14 13 CI rw 12 11 T5 CC rw 10 CT3 rw SFR (FF46H/A3H) 9 8 7 6 T5R rw 5 4 T5M rw Reset Value: 0000H 3 2 1 T5I rw 0 T5 T5 SC CLR rw rw T5 T5 T5 RC UDE UD rw rw rw Field T5SC Bits 15 Type rw Description Timer 5 Capture Mode Enable 0 Capture into register CAPREL Disabled 1 Capture into register CAPREL Enabled Timer T5 Clear Enable Bit 0 Timer T5 is not cleared on a capture event 1 Timer T5 is cleared on a capture event Register CAPREL Capture Trigger Selection (depending on bit CT3) 00 Capture disabled 01 Positive transition (rising edge) on CAPIN or any transition on T3IN 10 Negative transition (falling edge) on CAPIN or any transition on T3EUD 11 Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD T5CLR 14 rw CI [13:12] rw User's Manual GPT_X71, V2.0 14-40 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field T5CC Bits 11 Type rw Description Timer T5 Capture Correction 0 T5 is just captured without any correction 1 T5 is decremented by 1 before being captured Timer T3 Capture Trigger Enable 0 Capture trigger from input line CAPIN 1 Capture trigger from T3 input lines T3IN and/or T3EUD Timer T5 Remote Control 0 Timer T5 is controlled by its own run bit T5R 1 Timer T5 is controlled by the run bit T6R of core timer 6, not by bit T5R Timer T5 External Up/Down Enable1) 0 Input T5EUD is disconnected 1 Direction influenced by input T5EUD Timer T5 Up/Down Control1) 0 Timer T5 counts up 1 Timer T5 counts down Timer T5 Run Bit 0 Timer T5 stops 1 Timer T5 runs Note: This bit only controls timer T5 if bit T5RC = 0. T5M [5:3] rw Timer T5 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 1XX Reserved. Do not use this combination Timer T5 Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-16 for Timer Mode and Gated Timer Mode Table 14-12 for Counter Mode CT3 10 rw T5RC 9 rw T5UDE 8 rw T5UD 7 rw T5R 6 rw T5I [2:0] rw 1) See Table 14-11 for encoding of bits T5UD and T5UDE. User's Manual GPT_X71, V2.0 14-41 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer T5 Run Control The auxiliary timer T5 can be started or stopped by software in two different ways: * * Through the associated timer run bit (T5R). In this case it is required that the respective control bit T5RC = 0. Through the core timer's run bit (T6R). In this case the respective remote control bit must be set (T5RC = 1). The selected run bit is relevant in all operating modes of T5. Setting the bit will start the timer, clearing the bit stops the timer. In gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). Note: If remote control is selected T6R will start/stop timer T6 and the auxiliary timer T5 synchronously. 14.2.4 GPT2 Auxiliary Timer T5 Operating Modes The operation of the auxiliary timer in the basic operating modes is almost identical with the core timer's operation, with very few exceptions. Additionally, some combined operating modes can be selected. Timer T5 in Timer Mode Timer Mode for the auxiliary timer T5 is selected by setting its bitfield T5M in register T5CON to 000B. fT5 Count Auxiliary Timer T5 fGPT Prescaler T5IRQ BPS2 T5I T5R T6R 0 1 MUX Clear T5RC T5UD 0 =1 T5EUD T5UDE MCB05406_X4 MUX 1 Up/Down Figure 14-25 Block Diagram of Auxiliary Timer T5 in Timer Mode User's Manual GPT_X71, V2.0 14-42 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer T5 in Gated Timer Mode Gated timer mode for the auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 010B or 011B. Bit T5M.0 (T5CON.3) selects the active level of the gate input. Note: A transition of the gate signal at line T5IN does not cause an interrupt request. fGPT Prescaler Gate Ctrl. fT5 Count Auxiliary Timer T5 T5IRQ BPS2 T5IN T5I Clear T5R T6R 0 1 MUX T5RC T5UD 0 =1 T5EUD T5UDE MCB05407_X4 MUX 1 Up/Down Figure 14-26 Block Diagram of Auxiliary Timer T5 in Gated Timer Mode Note: There is no output toggle latch for T5. Start/stop of the auxiliary timer can be controlled locally or remotely. Timer T5 in Counter Mode Counter mode for auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 001B. In counter mode, the auxiliary timer can be clocked either by a transition at its external input line T5IN, or by a transition of timer T6's toggle latch T6OTL. The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. Bitfield T5I in control register T5CON selects the triggering transition (see Table 14-13). User's Manual GPT_X71, V2.0 14-43 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units T5IN T6 Toggle Latch 0 1 MUX Edge Count Auxiliary Timer T5 T5IRQ Select T5I.2 T5R T6R T5I 0 1 Clear MUX T5RC T5UD 0 =1 T5EUD T5UDE MCB05408_X4 MUX 1 Up/Down Figure 14-27 Block Diagram of Auxiliary Timer T5 in Counter Mode Table 14-13 GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection T5I X00 001 010 011 101 110 111 Triggering Edge for Counter Increment/Decrement None. Counter T5 is disabled Positive transition (rising edge) on T5IN Negative transition (falling edge) on T5IN Any transition (rising or falling edge) on T5IN Positive transition (rising edge) of T6 toggle latch T6OTL Negative transition (falling edge) of T6 toggle latch T6OTL Any transition (rising or falling edge) of T6 toggle latch T6OTL Note: Only state transitions of T6OTL which are caused by the overflows/underflows of T6 will trigger the counter function of T5. Modifications of T6OTL via software will NOT trigger the counter function of T5. For counter operation, pin T5IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T5IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.2.6. User's Manual GPT_X71, V2.0 14-44 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer T5. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T6OTL is selected to clock the auxiliary timer. * 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6. Thus, the two timers form a 32-bit timer. 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T6. This configuration forms a 33-bit timer (16-bit core timer + T6OTL + 16-bit auxiliary timer). As long as bit T6OTL is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. * The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T6, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. T6IRQ fGPT T6IN Operating Mode Control T6R Count Core Timer T6 Toggle Latch T6OUT BPS2 T6I Clear Up/Down T5IN 0 1 MUX Edge Count Auxiliary Timer T5 T5IRQ Select T5I.2 T5I T5R T6R 0 1 MUX Clear Up/Down T5RC MCA05409 Figure 14-28 Concatenation of Core Timer T6 and Auxiliary Timer T5 User's Manual GPT_X71, V2.0 14-45 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.5 GPT2 Register CAPREL Operating Modes The Capture/Reload register CAPREL can be used to capture the contents of timer T5, or to reload timer T6. A special mode facilitates the use of register CAPREL for both functions at the same time. This mode allows frequency multiplication. The capture function is triggered by the input pin CAPIN, or by GPT1 timer's T3 input lines T3IN and T3EUD. The reload function is triggered by an overflow or underflow of timer T6. In addition to the capture function, the capture trigger signal can also be used to clear the contents of timers T5 and T6 individually. The functions of register CAPREL are controlled via several bit(field)s in the timer control registers T5CON and T6CON. GPT2 Capture/Reload Register CAPREL in Capture Mode Capture mode for register CAPREL is selected by setting bit T5SC in control register T5CON (set bitfield CI in register T5CON to a non-zero value to select a trigger signal). In capture mode, the contents of the auxiliary timer T5 are latched into register CAPREL in response to a signal transition at the selected external input pin(s). Bit CT3 selects the external input line CAPIN or the input lines T3IN and/or T3EUD of GPT1 timer T3 as the source for a capture trigger. Either a positive, a negative, or both a positive and a negative transition at line CAPIN can be selected to trigger the capture function, or transitions on input T3IN or input T3EUD or both inputs, T3IN and T3EUD. The active edge is controlled by bitfield CI in register T5CON. Table 14-14 summarizes these options. Table 14-14 CAPREL Register Input Edge Selection CT3 X 0 0 0 1 1 1 CI 00 01 10 11 01 10 11 Triggering Signal/Edge for Capture Mode None. Capture Mode is disabled. Positive transition (rising edge) on CAPIN. Negative transition (falling edge) on CAPIN. Any transition (rising or falling edge) on CAPIN. Any transition (rising or falling edge) on T3IN. Any transition (rising or falling edge) on T3EUD. Any transition (rising or falling edge) on T3IN or T3EUD. User's Manual GPT_X71, V2.0 14-46 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Count Clock Clear Auxiliary Timer T5 T5IRQ Up/Down Edge CAPIN Select T5CLR 0 1 MUX Capture Capture Correction T5CC T3IN T3EUD Signal Select CT3 T5SC CAPREL Register CI CRIRQ Clear T6 T6CLR MCA05410 Figure 14-29 GPT2 Register CAPREL in Capture Mode When a selected trigger is detected, the contents of the auxiliary timer T5 are latched into register CAPREL and the interrupt request line CRIRQ is activated. The same event can optionally clear timer T5 and/or timer T6. This option is enabled by bit T5CLR in register T5CON and bit T6CLR in register T6CON, respectively. If TxCLR = 0 the contents of timer Tx is not affected by a capture. If TxCLR = 1 timer Tx is cleared after the current timer T5 value has been latched into register CAPREL. Note: Bit T5SC only controls whether or not a capture is performed. If T5SC is cleared the external input pin(s) can still be used to clear timer T5 and/or T6, or as external interrupt input(s). This interrupt is controlled by the CAPREL interrupt control register CRIC. When capture triggers T3IN or T3EUD are enabled (CT3 = 1), register CAPREL captures the contents of T5 upon transitions of the selected input(s). These values can be used to measure T3's input signals. This is useful, for example, when T3 operates in User's Manual GPT_X71, V2.0 14-47 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units incremental interface mode, in order to derive dynamic information (speed, acceleration) from the input signals. For capture mode operation, the selected pins CAPIN, T3IN, or T3EUD must be configured as input. To ensure that a transition of a trigger input signal applied to one of these inputs is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.2.6. GPT2 Capture/Reload Register CAPREL in Reload Mode Reload mode for register CAPREL is selected by setting bit T6SR in control register T6CON. In reload mode, the core timer T6 is reloaded with the contents of register CAPREL, triggered by an overflow or underflow of T6. This will not activate the interrupt request line CRIRQ associated with the CAPREL register. However, interrupt request line T6IRQ will be activated, indicating the overflow/underflow of T6. CAPREL Register Reload T6SR T6IRQ Count Clock Core Timer T6 Toggle Latch T6OUT T6OUF to T5 MCA05411 Up/Down Figure 14-30 GPT2 Register CAPREL in Reload Mode User's Manual GPT_X71, V2.0 14-48 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units GPT2 Capture/Reload Register CAPREL in Capture-And-Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits. This feature can be used to generate an output frequency that is a multiple of the input frequency. Count Clock Clear Up/Down Edge Auxiliary Timer T5 T5IRQ CAPIN Select T5CLR 0 1 MUX Capture Capture Correction T5CC T3IN T3EUD Edge CT3 Select T5SC CAPREL Register CRIRQ Reload Clear T6SR CI T6CLR Count Clock Core Timer T6 Toggle Latch T6IRQ T6OUT T6OUF to T5 MCA05412 Up/Down Figure 14-31 GPT2 Register CAPREL in Capture-And-Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, that means, more `ticks' within the time between two external events is required. For this purpose, the time between the external events is measured using timer T5 and the CAPREL register. Timer T5 runs in timer mode counting up with a frequency of e.g. fGPT/32. The external events are applied to pin CAPIN. When an external event occurs, User's Manual GPT_X71, V2.0 14-49 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units the contents of timer T5 are latched into register CAPREL and timer T5 is cleared (T5CLR = 1). Thus, register CAPREL always contains the correct time between two events, measured in timer T5 increments. Timer T6, which runs in timer mode counting down with a frequency of e.g. fGPT/4, uses the value in register CAPREL to perform a reload on underflow. This means, the value in register CAPREL represents the time between two underflows of timer T6, now measured in timer T6 increments. Since (in this example) timer T6 runs 8 times faster than timer T5, it will underflow 8 times within the time between two external events. Thus, the underflow signal of timer T6 generates 8 `ticks'. Upon each underflow, the interrupt request line T6IRQ will be activated and bit T6OTL will be toggled. The state of T6OTL may be output on pin T6OUT. This signal has 8 times more transitions than the signal which is applied to pin CAPIN. Note: The underflow signal of Timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units, which gives the user the possibility to set compare events based on a finer resolution than that of the external events. This connection is accomplished via signal T6OUF. Capture Correction A certain deviation of the output frequency is generated by the fact that timer T5 will count actual time units (e.g. T5 running at 1 MHz will count up to the value 64H/100D for a 10 kHz input signal), while T6OTL will only toggle upon an underflow of T6 (i.e. the transition from 0000H to FFFFH). In the above mentioned example, T6 would count down from 64H, so the underflow would occur after 101 timing ticks of T6. The actual output frequency then is 79.2 kHz, instead of the expected 80 kHz. This deviation can be compensated for by activating the Capture Correction (T5CC = 1). If capture correction is active, the contents of T5 are decremented by 1 before being captured. The described deviation is eliminated (in the example, T5 would count up to the value 64H/100D, but the CAPREL register will capture the decremented value 63H/99D, T6 would count exactly 100 ticks, and the output frequency is 80 kHz). User's Manual GPT_X71, V2.0 14-50 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.6 GPT2 Clock Signal Control All actions within the timer block GPT2 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield BPS2 in register T6CON (see Figure 14-20). The count clock can be generated in two different ways: * * Internal count clock, derived from GPT2's basic clock via a programmable prescaler, is used for (gated) timer mode. External count clock, derived from the timer's input pin(s), is used for counter mode. For both ways, the basic clock determines the maximum count frequency and the timer's resolution: Table 14-15 Basic Clock Selection for Block GPT2 Block Prescaler1) BPS2 = 01B BPS2 = 00B2) F(BPS2) =4 BPS2 = 11B F(BPS2) =8 BPS2 = 10B F(BPS2) = 16 Prescaling Factor F(BPS2) for GPT2: F(BPS2) = 2 Maximum External fGPT/4 Count Frequency Input Signal Stable Time 2) Default after reset. fGPT/8 4 x tGPT fGPT/16 8 x tGPT fGPT/32 16 x tGPT 2 x tGPT 1) Please note the non-linear encoding of bitfield BPS2. Internal Count Clock Generation In timer mode and gated timer mode, the count clock for each GPT2 timer is derived from the GPT2 basic clock by a programmable prescaler, controlled by bitfield TxI in the respective timer's control register TxCON. The count frequency fTx for a timer Tx and its resolution rTx are scaled linearly with lower clock frequencies, as can be seen from the following formula: f Tx = ------------------------------------------- F ( BPS2 ) x 2 f GPT -------------------------------------------r Tx [ s ] = F ( BPS2 ) x 2 f GPT [ MHz ] (14.2) The effective count frequency depends on the common module clock prescaler factor F(BPS2) as well as on the individual input prescaler factor 2 User's Manual GPT_X71, V2.0 14-51 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Table 14-16 GPT2 Overall Prescaler Factors for Internal Count Clock Individual Prescaler for Tx TxI = 000B TxI = 001B TxI = 010B TxI = 011B TxI = 100B TxI = 101B TxI = 110B TxI = 111B Common Prescaler for Module Clock1) BPS2 = 01B 2 4 8 16 32 64 128 256 BPS2 = 00B 4 8 16 32 64 128 256 512 BPS2 = 11B 8 16 32 64 128 256 512 1024 BPS2 = 10B 16 32 64 128 256 512 1024 2048 1) Please note the non-linear encoding of bitfield BPS2. Table 14-17 lists a timer's parameters (such as count frequency, resolution, and period) resulting from the selected overall prescaler factor and the applied system frequency. Note that some numbers may be rounded. Table 14-17 GPT2 Timer Parameters System Clock = 10 MHz Frequency 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.06 kHz 19.53 kHz 9.77 kHz 4.88 kHz Resolution Period 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s Overall Divider Factor System Clock = 40 MHz Frequency Resolution Period 20.0 MHz 10.0 MHz 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 3.28 ms 6.55 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1.678 s 3.355 s 13.11 ms 2 26.21 ms 4 52.43 ms 8 104.9 ms 16 209.7 ms 32 419.4 ms 64 838.9 ms 128 1.678 s 3.355 s 6.711 s 13.42 s 256 512 1024 2048 156.25 kHz 6.4 s 78.125 kHz 12.8 s 39.06 kHz 19.53 kHz 25.6 s 51.2 s User's Manual GPT_X71, V2.0 14-52 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units External Count Clock Input The external input signals of the GPT2 block are sampled with the GPT2 basic clock (see Figure 14-20). To ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. A signal transition is recognized if two subsequent samples of the input signal represent different levels. Therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than half the basic clock. Table 14-18 summarizes the resulting requirements for external GPT2 input signals. Table 14-18 GPT2 External Input Signal Limits System Clock = 10 MHz Input Max. Input Min. Level Frequ. Frequency Hold Time Factor 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 200 ns 400 ns 800 ns 1.6 s GPT2 Divider BPS1 01B 00B 11B 10B System Clock = 40 MHz Input Phase Max. Input Min. Level Duration Frequency Hold Time 2 x tGPT 4 x tGPT 8 x tGPT 16 x tGPT 10.0 MHz 5.0 MHz 2.5 MHz 1.25 MHz 50 ns 100 ns 200 ns 400 ns fGPT/4 fGPT/8 fGPT/16 fGPT/32 These limitations are valid for all external input signals to GPT2, including the external count signals in counter mode and the gate input signals in gated timer mode. User's Manual GPT_X71, V2.0 14-53 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.7 GPT2 Timer Registers GPT12E_Tx Timer x Count Register 15 14 13 12 11 10 SFR (FE4xH/2yH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 Txvalue rwh Table 14-19 GPT1 Timer Register Locations Timer Register T5 T6 Physical Address FE46H FE48H 8-Bit Address 23H 24H GPT12E_CAPREL Capture/Reload Register 15 14 13 12 11 10 SFR (FE4AH/25H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 Capture/Reloadvalue rwh User's Manual GPT_X71, V2.0 14-54 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.8 Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000H to FFFFH (when counting down), its interrupt request flag (T5IR or T6IR) in register TxIC will be set. Whenever a transition according to the selection in bit field CI is detected at pin CAPIN, interrupt request flag CRIR in register CRIC is set. Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector (T5INT, T6INT or CRINT) or trigger a PEC service, if the respective interrupt enable bit (T5IE or T6IE in register TxIC, CRIE in register CRIC) is set. There is an interrupt control register for each of the two timers and for the CAPREL register. GPT12E_T5IC Timer 5 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF66H/B3H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T5IR T5IE rw rwh rw ILVL rw GLVL rw GPT12E_T6IC Timer 6 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF68H/B4H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T6IR T6IE rw rwh rw ILVL rw GLVL rw GPT12E_CRIC CAPREL Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF6AH/B5H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX CRIR CRIE rw rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual GPT_X71, V2.0 14-55 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.3 Interfaces of the GPT Module Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2 are connected to their environment in two basic ways (see Figure 14-32): * * Internal connections interface the timers with on-chip resources such as clock generation unit, interrupt controller, or other timers. External connections interface the timers with external resources via port pins. System Control Unit f GPT GPTDIS T2EUD T4EUD T2IN P5.15 P5.14 P3.7 P3.6 Port Logic for P3 and P5 P3.5 P3.4 P3.3 P5.13 P5.12 P5.11 P5.10 P3.2 P3.1 mc_gpt0105_modinterface_x.vsd T2IRQ T3IRQ Interrupt Control Unit T4IRQ T5IRQ T6IRQ CRIRQ T3IN T4IN General Purpose Timer Units T3EUD T3OUT T5IN T6IN T5EUD T6EUD CAPCOM Units T6OUF CAPIN T6OUT Figure 14-32 GPT Module Interfaces Port pins to be used for timer input signals must be switched to input, the respective direction control bits must be cleared (DPx.y = 0). Port pins to be used for timer output signals must be switched to output, the respective direction control bits must be set (DPx.y = 1). The alternate timer output signal must be selected for these pins via the respective alternate select registers (see Chapter 7). Interrupt nodes to be used for timer interrupt requests must be enabled and programmed to a specific interrupt level. User's Manual GPT_X71, V2.0 14-56 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15 Real Time Clock The Real Time Clock (RTC) module of the XC167 basically consists of a chain of prescalers and timers. Its count clock is derived from the auxiliary oscillator or from the prescaled main oscillator. The RTC serves various purposes: * * * 48-bit timer for long term measurements System clock to determine the current time and date (the RTC's structure supports the direct representation of time and date) Cyclic time based interrupt (can be generated by any timer of the chain) A number of programming options as well as interrupt request signals adjust the operation of the RTC to the application's requirements. The RTC can continue its operation while the XC167 is in a power-saving mode, such that real time date and time information is provided. C on trol R egisters D ata R egisters C ounter R e gisters Inte rru pt C ontrol R TC _ C O N SYSCON0 SYSCON3 E E E R TC _T 14R E L R TC _R E LH R TC _R E LL E E E R T C _T 14 R T C _R T C H R T C _R T C L E E E R T C _IS N C R T C _IC E E R T C _C O N SYSCON0 SYSCON3 R T C _IS N C R T C _IC R ea l T im e C lock C ontrol R egister G eneral S yste m C ontrol R egister P ow er M a nagem ent C ontrol R eg. Interrupt S ubnode C ontrol R egister R T C Interrupt C ontrol R egister R T C _T 14 R T C _T 14R E L R T C _R T C H /L R T C _R E LH /L T im er T 14 C ount R eg ister T im er T 14 R eload R egister R T C C ount R eg isters, H igh/Low R T C R eload R eg., H igh/Low m ca04463_xc .vs d Figure 15-1 SFRs Associated with the RTC Module The RTC module consists of a chain of 3 divider blocks: * * * a selectable 8:1 divider (on - off) the reloadable 16-bit timer T14 the 32-bit RTC timer block (accessible via RTC_RTCH and RTC_RTCL), made of: - the reloadable 10-bit timer CNT0 - the reloadable 6-bit timer CNT1 - the reloadable 6-bit timer CNT2 - the reloadable 10-bit timer CNT3 All timers count upwards. Each of the five timers can generate an interrupt request. All requests are combined to a common node request. Note: The RTC registers are not affected by a system reset in order to maintain the correct system time even when intermediate resets are executed. User's Manual RTC_X8, V2.1 15-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.1 Defining the RTC Time Base The timer chain of the RTC is clocked with the count clock signal fRTC which is derived from the auxiliary oscillator or from the prescaled main oscillator (see Figure 15-2 and Figure 15-3). Optionally prescaled by a factor of 8, this is the basic RTC clock. Depending on the operating mode, timer T14 may provide the count increments used by the application and thus determine the input frequency of the RTC timer, that is, the RTC time base (see also Table 15-3). The RTC is also supplied with the system clock fSYS of the XC167. This clock signal is used to control the RTC's logic blocks and its bus interface. To synchronize properly to the count clock, the system clock must run at least four times faster than the count clock, this means fSYS 4 x fCNT. REFCLK Aux. OSC RUN 1 0 PRE Async Mode 1 0 RTCCM SYSCON0.14 MCB05413 fOSCa >1 fRTCa fRTCm MUX fRTC 8:1 MUX fCNT RTC Count Clock Main OSC fOSCm 32:1 Clock Generation Unit fSYS MUX Sync Mode RTC Module Clock Figure 15-2 RTC Clock Supply Block Diagram For an example, Table 15-1 lists the interrupt period range and the T14 reload values (for a time base of 1 s and 1 ms): Table 15-1 Oscillator Frequency 32.768 kHz RTC Time Base Examples T14 Intr. Period Min. Max. 30.52 s 16.0 s Reload Value A T14REL 8000H/F000H Base 1.000 s Reload Value B T14REL FFDFH/ FFFCH Base 1.007 ms/ 0.977 ms Note: Select one value from the reload value pairs, depending if the 8:1 prescaler is disabled/enabled. User's Manual RTC_X8, V2.1 15-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock Asynchronous Operation When the system clock frequency becomes lower than 4 x fCNT proper synchronization is not possible and count events may be missed. When the XC167 enters e.g. sleep mode the system clock stops completely and the RTC would stop counting. In these cases the RTC can be switched to Asynchronous Mode (by setting bit RTCCM in register SYSCON0). In this mode the count registers are directly controlled by the count clock independent of the system clock (hence the name). Asynchronous operation ensures correct time-keeping even during sleep mode or powerdown mode. However, as no synchronization between the count registers and the bus interface can be maintained in asynchronous mode, the RTC registers cannot be written. Read accesses may interfere with count events and, therefore, must be verified (e.g. by reading the same value with three consecutive read accesses). Note: The access restrictions in asynchronous mode are only meaningful if the system clock is not switched off, of course. Switching Clocking Modes The clocking mode of the RTC (synchronous or asynchronous) is selected via bit RTCCM in register SYSCON0. After reset, the RTC operates in Synchronous Mode (RTCCM = 0) with the 8:1 prescaler enabled. The selected clocking mode also affects the access to RTC registers. Bit ACCPOS in register RTC_CON indicates if full register access is possible (ACCPOS = 1, default after reset) or not (ACCPOS = 0). This also indicates the current clocking mode. Attention: Software should poll bit ACCPOS to determine the proper transition to the intended clocking mode. After switching to Asynchronous Mode (RTCCM = 1), bit ACCPOS = 0 indicates proper operation in Asynchronous Mode. In this case the system clock can be stopped or reduced. After switching to Synchronous Mode, (RTCCM = 0), bit ACCPOS = 1 indicates proper operation in Synchronous Mode. In this case the RTC registers can again be accessed properly (read and write). Note: The RTC might lose a counting event (edge of fCNT) when switching from synchronous mode to asynchronous mode while the 8:1 prescaler is disabled. For these applications it is, therefore, recommended to set up the RTC with the 8:1 prescaler enabled. User's Manual RTC_X8, V2.1 15-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock Increased RTC Accuracy through Software Correction The accuracy of the XC167's RTC is determined by the oscillator frequency and by the respective prescaling factor (excluding or including T14 and the 8:1 prescaler). The accuracy limit generated by the prescaler is due to the quantization of a binary counter (where the average is zero), while the accuracy limit generated by the oscillator frequency is due to the difference between the ideal and real frequencies (and therefore accumulates over time). This effect is predictable and can be compensated. The total accuracy of the RTC can be further increased via software for specific applications that demand a high time accuracy. The key to the improved accuracy is knowledge of the exact oscillator frequency. The relation of this frequency to the expected ideal frequency is a measure of the RTC's deviation. The number of cycles, N, after which this deviation causes an error of 1 cycle can be easily computed. So, the only action is to correct the count by 1 after each series of N cycles. The correction may be made cyclically, for instance, within an interrupt service routine, or by evaluating a formula when the RTC registers are read (for this the respective "last" RTC value must be available somewhere). Note: For the majority of applications, however, the standard accuracy provided by the RTC's structure will be more than sufficient. Adjusting the current RTC value would require reading and then writing the complete 48-bit value. This can only be accomplished by three successive accesses each. To avoid the hassle of reading/writing multi-word values, the RTC incorporates a correction option to simply add or suppress one count pulse. This is done by setting bit T14INC or T14DEC, respectively, in register RTC_CON. This will add an extra count pulse (T14INC) upon the next count event, or suppress the next count event (T14DEC). The respective bit remains set until its associated action has been performed and is automatically cleared by hardware after this event. Note: Setting both bits, T14INC and T14DEC, at the same time will have no effect on the count values. User's Manual RTC_X8, V2.1 15-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.2 RTC Run Control If the RTC shall operate bit RUN in register RTC_CON must be set (default after reset). Bit RUN can be cleared, for example, to exclude certain operation phases from time keeping. The RTC can be completely disabled by setting the corresponding bit RTCDIS in register SYSCON3. Note: A valid count clock is required for proper RTC operation, of course. A reset for the RTC is triggered via software by setting bit RTCRST in register SYSCON0. In this case all RTC registers are set to their initial values and bit RTCRST is cleared automatically. A normal system reset does not affect the RTC registers and its operation (RTC_IC will be reset, however). The initialization software must ensure the proper RTC operating mode. The RTC control register RTC_CON selects the basic operation of the RTC module. RTC_CON Control Register 15 ACC POS rh 14 13 12 11 10 - ESFR (F110H/88H) 9 8 7 6 5 4 Reset Value: 8003H 3 2 1 0 REF T14 T14 PRE RUN CLK INC DEC rw rwh rwh rw rw Field ACCPOS Bits 15 Type rh Description RTC Register Access Possible 0 No write access is possible, only asynchronous reads 1 Registers can be read and written Reference Clock Source 0 The RTC count clock is derived from the auxiliary oscillator (fOSCa) 1 The RTC count clock is derived from the main oscillator (fOSCm/32) Increment Timer T14 Value Setting this bit to 1 adds one count pulse upon the next count event, thus incrementing T14. This bit is cleared by hardware after incrementation. Decrement Timer T14 Value Setting this bit to 1 suppresses the next count event, thus decrementing T14. This bit is cleared by hardware after decrementation. REFCLK 4 rw T14INC 3 rwh T14DEC 2 rwh User's Manual RTC_X8, V2.1 15-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock Field PRE Bits 1 Type rw Description RTC Input Source Prescaler Enable 0 Prescaler disabled, T14 clocked with fRTC 1 Prescaler enabled, T14 clocked with fRTC/8 RTC Run Bit 0 RTC stopped 1 RTC runs RUN 0 rw User's Manual RTC_X8, V2.1 15-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.3 RTC Operating Modes The RTC can be configured for several operating modes according to the purpose it is meant to serve. These operating modes are configured by selecting appropriate reload values and interrupt signals. PRE RUN fRTC 8 1 MUX 0 R TC IN T Interru pt S u b N od e CNT IN T 0 CNT IN T 1 CNT IN T2 CNT IN T 3 R EL-R egister T14REL 1 0 B its 6 B its 6 B its 1 0 B its fCNT T14 T14-R egister 1 0 B its 6 B its 6 B its 1 0 B its C N T-R egister m cb04805_x c.vsd Figure 15-3 RTC Block Diagram RTC Register Access The actual value of the RTC is indicated by the three registers T14, RTCL, and RTCH. As these registers are concatenated to build the RTC counter chain, internal overflows occur while the RTC is running. When reading or writing the RTC value, such internal overflows must be taken into account to avoid reading/writing corrupted values. Care must be taken, when reading the timer(s), as this requires up to three read accesses to the different registers with an inherent time delay between the accesses. An overflow from T14 to RTCL and/or from RTCL to RTCH might occur between the accesses, which needs to be taken into account appropriately. For example, reading/writing 0000H to RTCH and then accessing RTCL could produce a corrupted value as RTCL may overflow before it can be accessed. In this case, RTCH would be 0001H. The same precautions must be taken for T14 and T14REL. User's Manual RTC_X8, V2.1 15-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock Timer T14 and its reload register are accessed via dedicated locations. The four RTC counters CNT3 ... CNT0 are accessed via the two 16-bit RTC timer registers, RTCH and RTCL. The associated four reload values REL3 ... REL0 are accessed via the two 16-bit RTC reload registers, RELH and RELL. Table 15-2 Register Locations for Timer T14 Long/Short Address F0D2H/69H F0D0H/68H Reset Value 0000H 0000H Notes 16-bit timer, can be used as prescaler for the RTC block Timer T14 reload register Register Name RTC_T14 RTC_T14REL RTC_RTCH RTC Timer High Register 15 14 13 12 11 10 ESFR (F0D6H/6BH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CNT3 rwh CNT2 rwh RTC_RTCL RTC Timer Low Register 15 14 13 12 11 10 ESFR (F0D4H/6AH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CNT1 rwh CNT0 rwh Field CNTx (x = 3 ... 0) Bits Type Description RTC Timer Count Section CNTx An overflow of this bitfield triggers a count pulse to the next count section CNTx+1 (except for CNT3) followed by a reload of CNTx from bitfield RELx. In addition, an interrupt request is triggered. [15:6] rwh [5:0] [15:10] [9:0] User's Manual RTC_X8, V2.1 15-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock RTC_RELH RTC Reload High Register 15 14 13 12 11 10 ESFR (F0CEH/67H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 REL3 rw REL2 rw RTC_RELL RTC Reload Low Register 15 14 13 12 11 10 ESFR (F0CCH/66H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 REL1 rw REL0 rw Field RELx (x = 3 ... 0) Bits Type Description RTC Reload Value RELx This bitfield is copied to bitfield CNTx upon an overflow of count section CNTx. [15:6] rw [5:0] [15:10] [9:0] Note: The registers of the RTC receive their reset values only upon a specific RTC reset. This reset is not triggered upon a system reset, but via software. User's Manual RTC_X8, V2.1 15-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.3.1 48-bit Timer Operation The concatenation of timers T14 and COUNT0 ... COUNT3 can be regarded as a 48-bit timer which is clocked with the RTC input frequency, optionally divided by the prescaler. The reload registers T14REL, RELL, and RELH must be cleared to produce a true binary 48-bit timer. However, any other reload value may be used. Reload values other than zero must be used carefully, due to the individual sections of the RTC timer with their own individual overflows and reload values. The maximum usable timespan is 248 ( 1014) T14 input clocks (assuming no prescaler), which would equal more than 200 years at an oscillator frequency of 32 kHz. 15.3.2 System Clock Operation A real time system clock can be maintained that keeps on running also during power saving modes (optionally) and indicates the current time and date. This is possible because the RTC module is not affected by a system reset1). The resolution for this clock information is determined by the input clock of timer T14. By selecting appropriate reload values each cascaded timer can represent directly a part of the current time and/or date. Due to its width, T14 can adjust the RTC to the intended range of operation (time or date). The maximum usable timespan is achieved when T14REL is loaded with 0000H and so T14 divides by 216. System Clock Example The RTC count clock is fOSCa (8:1 prescaler off). By selecting appropriate reload values the RTC timers directly indicate the current time (see Figure 15-4 and Table 15-3). 3E8H REL3 04H REL2 04H REL1 018H REL0 FFDFH T14REL fCNT = CNT3 Hours CNT2 Minutes CNT1 Seconds CNT0 1/1000 Seconds T14 Prescaler 32.768 kHz MCA05414 Figure 15-4 RTC Configuration Example Note: This setup can generate an interrupt request every millisecond, every second, every minute, every hour, or every day. 1) After a power on reset, however, the RTC registers are undefined. User's Manual RTC_X8, V2.1 15-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock Each timer in the chain divides the clock by (2 1) T14 errors in the first example (ms) can be compensated either by choosing an adapted value for REL0, or by using software correction. 15.3.3 Day of the Week Cyclic Interrupt Generation The RTC module can generate an interrupt request whenever one of the timers overflows and is reloaded. This interrupt request may be used, for example, to provide a system time tick independent of the CPU frequency without loading the general purpose timers, or to wake-up regularly from sleep mode. The interrupt cycle time can be adjusted by choosing appropriate reload values and by enabling the appropriate interrupt request. In this mode, the other operating modes can be combined. For example, a reload value of T14REL = F9C0H (216 - 1600) generates a T14 interrupt request every 50 ms to wakeup the system regularly. Still the subsequent timers can be configured to represent the time or build a binary counter, however with a different time base. User's Manual RTC_X8, V2.1 15-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.4 RTC Interrupt Generation The overflow signals of each timer of the RTC timer chain can generate an interrupt request. The RTC's interrupt subnode control register ISNC combines these requests to activate the common RTC interrupt request line RTC_IRQ. Each timer overflow sets its associated request flag in register ISNC. Individual enable bits for each request flag determine whether this request also activates the common interrupt line. The enabled requests are ORed together on this line (see Figure 15-5). The interrupt handler can determine the source of an interrupt request via the specific request flags and must clear them after appropriate processing (not cleared by hardware). The common node request bit is automatically cleared when the interrupt handler is vectored to. Note: If only one source is enabled, no additional software check is required, of course. Both the individual request and the common interrupt node must be enabled. Register RTC_ISNC CNT3 Overflow Set SW Clear Set SW Clear Set SW Clear Set SW Clear Set SW Clear CNT3 IR & CNT3 IE CNT2 Overflow CNT2 IR & CNT2 IE _ >1 CNT1 Overflow CNT1 IR & CNT1 IE Interrupt Request RTC_IRQ CNT0 Overflow CNT0 IR & CNT0 IE T14 Overflow T14 IR & T14 IE MCB05415 Figure 15-5 Interrupt Block Diagram User's Manual RTC_X8, V2.1 15-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock RTC_ISNC Interrupt Subnode Ctrl. Reg. 15 14 13 12 11 10 - ESFR (F10CH/86H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CNT CNT CNT CNT CNT CNT CNT CNT T14 T14 3IR 3IE 2IR 2IE 1IR 1IE 0IR 0IE IR IE rwh rw rwh rw rwh rw rwh rw rwh rw Field CNTxIR (x = 3 ... 0) CNTxIE (x = 3 ... 0) T14IR Bits Type Description Section CNTx Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request Section CNTx Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request is enabled T14 Overflow Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request T14 Overflow Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request is enabled 9, 7, 5, rwh 3 8, 6, 4, rw 2 1 rwh T14IE 0 rw Note: The interrupt request flags in register ISNC must be cleared by software. They are not cleared automatically when the service routine is entered. RTC_IC RTC Interrupt Ctrl. Reg. 15 14 13 12 11 10 - ESFR (F1A0H/D0H) 9 8 GPX rw 7 6 5 4 Reset Value: 0000H 3 2 1 0 RTC RTC IR IE rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Register RTC_IC is not part of the RTC module and is reset with any system reset. User's Manual RTC_X8, V2.1 15-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16 The Analog/Digital Converter The XC167 provides an Analog/Digital Converter with 8-bit or 10-bit resolution and a sample & hold circuit on-chip. An input multiplexer selects between up to 16 analog input channels (alternate functions of Port 5) either via software (fixed channel modes) or automatically (auto scan modes). To fulfill most requirements of embedded control applications the ADC supports the following conversion modes: * * * * * * Fixed Channel Single Conversion produces just one result from the selected channel Fixed Channel Continuous Conversion repeatedly converts the selected channel Auto Scan Single Conversion produces one result from each of a selected group of channels Auto Scan Continuous Conversion repeatedly converts the selected group of channels Wait for ADDAT Read Mode start a conversion automatically when the previous result was read Channel Injection Mode start a conversion when a hardware trigger occurs, can insert the conversion of a specific channel into a group conversion (auto scan) A set of SFRs and port pins provide access to control functions and results of the ADC. The enhanced-mode registers provide more detailed control functions for the ADC. Data Registers ADC_DAT ADC_DAT2 E Control Registers ADC_CON ADC_CON1 ADC_CTR0 ADC_CTR2 ADC_CTR2IN Compatibility Mode: ADC_CON ADC Control Register ADC_CON1 ADC Control Register 1 Enhanced Mode: ADC_CTR0 ADC Control Register 0 ADC_CTR2 ADC Control Register 2 ADC_CTR2IN ADC Control Injection Register ADC_DAT ADC_DAT2 ADC_CIC ADC_EIC P5 P5DIDIS SYSCON3 ADC Result Register ADC Injection Result Register ADC End-of-Conversion Intr. Reg. ADC Conversion-Error Intr. Reg. Port 5 Analog Input Port (AN15...AN0) Port 5 Digital Input Disable Reg. mc_adc0102_registers_x7.vsd Interrupt Control ADC_CIC ADC_EIC System Registers P5 P5DIDIS E Figure 16-1 SFRs and Port Pins Associated with the A/D Converter User's Manual ADC_X71, V2.1 16-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter The external analog reference voltages VAREF and VAGND are fixed. The separate supply for the ADC reduces the interference with other digital signals. The reference voltages must be stable during the reset calibration phase and during an entire conversion, to achieve a maximum of accuracy. The sample time as well as the conversion time is programmable, so the ADC can be adjusted to the internal resistances of the analog sources and/or the analog reference voltage supply (you may also want to refer to application note AP2428). CTR0 CON CON1 CTR2 CTR2IN Injection Requests MUX Conversion Control ADC_CIRQ ADC_EIRQ AN0 MUX Sample & Hold AN15 8/10-bit Capacitive Network Conversion DAT DAT2 MCB05416_X7 Figure 16-2 Analog/Digital Converter Block Diagram The ADC is implemented as a capacitive network using successive approximation conversion. A conversion consists of 3 phases. * * During the sample phase, the capacitive network is connected to the selected analog input and is charged or discharged to the voltage of the analog signal. During the actual conversion phase, the network is disconnected from the analog input and is repeatedly charged or discharged via VAREF during the steps of successive approximation. After the (optional) post-calibration phase (to adjust the network to changing conditions such as temperature) the result is written to the result register and an interrupt request is generated. * There are two sets of control, data, and status registers, one set for compatibility mode and one set for enhanced mode. Only one of these register sets may be active at a given time. As most of the bits and bitfields of the registers of the two sets control the same functionality or control the functionality in a very similar way, the following description is organized according to the functionality, not according to the two register sets. User's Manual ADC_X71, V2.1 16-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.1 Mode Selection The analog input channels AN15 ... AN0 are alternate functions of Port 5 which is an input-only port. The Port 5 lines may either be used as analog or digital inputs. For pins that shall be used as analog inputs it is recommended to disable the digital input stage via register P5DIDIS. This avoids undesired cross currents and switching noise while the (analog) input signal level is between VIL and VIH. The functions of the A/D converter are controlled by two sets of bit-addressable control registers. In compatibility mode, registers ADC_CON and ADC_CON1 are used, in enhanced mode, registers ADC_CTR0, ADC_CTR2, and ADC_CTR2IN are used. Their bitfields specify the analog channel to be acted upon, the conversion mode, and also reflect the status of the converter. 16.1.1 Compatibility Mode In compatibility mode (MD = 0), registers ADC_CON and ADC_CON1 select the basic functions. The register layout is compatible with previous versions of the ADC module, while providing limited options. ADC_CON ADC Control Register 15 14 13 12 11 10 SFR (FFA0H/D0H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 ADCTC rw ADSTC rw AD AD CRQ CIN rwh rw AD AD AD WR BSY ST rw rwh rwh ADM rw ADCH rw Field ADCTC Bits Type Function ADC Conversion Time Control (Defines the ADC basic conversion clock fBC) 00 fBC = fADC/4 01 fBC = fADC/2 10 fBC = fADC/16 11 fBC = fADC/8 ADC Sample Time Control (Defines the ADC sample time in a certain range) 00 tBC x 8 01 tBC x 16 10 tBC x 32 11 tBC x 64 ADC Channel Injection Request Flag ADC Channel Injection Enable 16-3 V2.0, 2004-04 [15:14] rw ADSTC [13:12] rw ADCRQ ADCIN User's Manual ADC_X71, V2.1 11 10 rwh rw XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Field ADWR ADBSY Bits 9 8 Type rw rh Function ADC Wait for Read Control ADC Busy Flag 0 ADC is idle 1 A conversion is active ADC Start Bit 0 Stop a running conversion 1 Start conversion(s) ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADC Analog Channel Input Selection Selects the (first) ADC channel which is to be converted. ADST 7 rwh ADM [5:4] rw ADCH [3:0] rw ADC_CON1 ADC Control Register 1 15 ICST rw 14 13 12 11 10 SFR (FFA6H/D3H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SAM CAL RES PLE rh rh rw ADCTC rw ADSTC rw Field ICST Bits 15 Type rw Description Improved Conversion and Sample Timing Selects the active timing control bitfields 0 Standard conversion and sample time control, 2-bit fields in ADC_CON (default after reset) 1 Improved conversion and sample time control, 6-bit fields in ADC_CON1 Sample Phase Status Flag 0 A/D Converter is not in sampling 1 A/D Converter is currently in the sample phase Reset Calibration Phase Status Flag 0 A/D Converter is not in calibration phase 1 A/D Converter is in calibration phase SAMPLE 14 rh CAL 13 rh User's Manual ADC_X71, V2.1 16-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Field RES Bits 12 Type rw Description Conversion Resolution Control 0 10-bit resolution (default after reset) 1 8-bit resolution ADC Conversion Time Control Defines the ADC basic conversion clock: fBC = fADC / ( ADCTC [11:6] rw ADSTC [5:0] rw Note: The limit values for fBC (see data sheet) must not be exceeded when selecting ADCTC and fADC. 16.1.2 Enhanced Mode In enhanced mode (MD = 1), registers ADC_CTR0, ADC_CTR2, and ADC_CTR2IN select the basic functions. The register layout differs from the compatibility-mode layout, but this mode provides more options. Conversion timing is selected via registers ADC_CTR2(IN), where ADC_CTR2 controls standard conversions and ADC_CTR2IN controls injected conversions. ADC_CTR0 ADC Control Register 0 15 MD rw 14 SAM PLE rh 13 12 11 10 SFR (FFBEH/DFH) 9 8 7 6 5 4 CAL OFF rw Reset Value: 1000H 3 2 1 0 ADCTS rw AD AD CRQ CIN rwh rw AD AD AD WR BSY ST rw rh rwh ADM rw ADCH rw Field MD Bits 15 Type rw Description Mode Control 0 Compatibility Mode 1 Enhanced Mode Note: Any modification of control bit MD is forbidden while a conversion is currently running. User software must take care. SAMPLE 14 rh Sample Phase Status Flag 0 A/D Converter is not in sample phase 1 A/D Converter in sample phase User's Manual ADC_X71, V2.1 16-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Field ADCTS Bits Type Description Channel Injection Trigger Input Select 00 Channel injection trigger input disabled 01 Trigger input CAPCOM2 selected 10 Trigger input CAPCOM6 selected 11 Reserved Note: Reset value of bitfield ADCTS is 01B for compatibility purposes. ADCRQ ADCIN ADWR ADBSY 11 10 9 8 rwh rw rw rh Channel Injection Request Flag Channel Injection Enable Control Wait for Read Control Busy Flag 0 ADC is idle 1 A conversion is active ADC Start/Stop Control 0 Stop a running conversion 1 Start conversion(s) Mode Selection Control 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion Calibration Disable Control 0 Calibration cycles are executed 1 Calibration is disabled (off) Note: This control bit is active in both compatibility and enhanced mode. ADCH [3:0] rw Analog Input Channel Selection Selects the (first) ADC channel which is to be converted [13:12] rw ADST 7 rwh ADM [6:5] rw CALOFF 4 rw User's Manual ADC_X71, V2.1 16-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter ADC_CTR2 ADC Control Register 2 15 14 13 12 11 10 ESFR (F09CH/4EH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 RES rw ADCTC rw ADSTC rw ADC_CTR2IN Injection Control Register 2 15 r 14 13 12 11 10 ESFR (F09EH/4FH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 RES rw ADCTC rw ADSTC rw Field RES Bits Type Description Converter Resolution Control 00 10-bit resolution (default after reset) 01 8-bit resolution 1x Reserved ADC Conversion Time Control Defines the ADC basic conversion clock: fBC = fADC / ( [13:12] rw ADCTC [11:6] rw ADSTC [5:0] rw Note: The limit values for fBC (see data sheet) must not be exceeded when selecting ADCTC and fADC. User's Manual ADC_X71, V2.1 16-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2 ADC Operation Channel Selection, ADCH Bitfield ADCH controls the input channel multiplexer logic. In the Single Channel Modes, it specifies the analog input channel which is to be converted. In the Auto Scan Modes, it specifies the highest channel number to be converted in the auto scan round. ADCH may be changed while a conversion is in progress. The new value will go into effect after the current conversion is finished in the fixed channel modes, or after the current conversion round is finished in the auto scan modes. ADC Flags, ADBSY, SAMPLE The ADC Busy Status Flag is set when the ADC is started (by setting ADST) and remains set as long as the ADC performs conversions or calibration cycles. ADBSY is cleared when the ADC is idle, meaning there are no conversion or calibration operations in progress. Bit SAMPLE is set during the sample phase. ADC Start/Stop Control, ADST Bit ADST is used to start or to stop the ADC. A single conversion or a conversion sequence is started by setting bit ADST. The busy flag ADBSY will be set and the converter then selects and samples the input channel, which is specified by the channel selection field ADCH. The sampled level will then be held internally during the conversion. When the conversion of this channel is complete, the result together with the number of the converted channel is transferred into the result register and the interrupt request is generated. The conversion result is placed into bitfield ADRES. ADST remains set until cleared either by hardware or by software. Hardware clears the bit dependent on the conversion mode: * * In Fixed Channel Single Conversion mode, ADST is cleared after the conversion of the specified channel is finished. In Auto Scan Single Conversion mode, ADST is cleared after the conversion of channel 0 is finished. Note: In the continuous conversion modes, ADST is never cleared by hardware. Stopping the ADC via software is performed by clearing bit ADST. The reaction of the ADC depends on the conversion mode: * * In Fixed Channel Single Conversion mode, the ADC finishes the conversion and then stops. There is no difference to the operation if ADST was not cleared by software. In Fixed Channel Continuous Conversion mode, the ADC finishes the current conversion and then stops. This is the usual way to terminate this conversion mode. 16-8 V2.0, 2004-04 User's Manual ADC_X71, V2.1 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter * In Auto Scan Single Conversion mode, the ADC continues the auto scan round until the conversion of channel 0 is finished, then it stops. There is no difference to the operation if ADST was not cleared by software. In Auto Scan Continuous Conversion mode, the ADC continues the auto scan round until the conversion of channel 0 is finished, then it stops. This is the usual way to terminate this conversion mode. * A restart of the ADC can be performed by clearing and then setting bit ADST. This sequence will abort the current conversion and restart the ADC with the new parameters given in the control registers. Conversion Mode Selection, ADM Bitfield ADM selects the conversion mode of the A/D converter, as listed in Table 16-1. Table 16-1 ADM 00 01 10 11 A/D Converter Conversion Mode Description Fixed Channel Single Conversion Fixed Channel Continuous Conversion Auto Scan Single Conversion Auto Scan Continuous Conversion While a conversion is in progress, the mode selection field ADM and the channel selection field ADCH may be changed. ADM will be evaluated after the current conversion. ADCH will be evaluated after the current conversion (fixed channel modes) or after the current conversion sequence (auto scan modes). Conversion Resolution Control, RES The ADC can produce either a 10-bit result (RES = 0) or an 8-bit result (RES = 1). Depending on the application's needs a higher conversion speed (an 8-bit conversion requires less conversion time) or a higher resolution can be chosen. User's Manual ADC_X71, V2.1 16-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Conversion Result The result of a conversion is stored in the result register ADC_DAT, or in register ADC_DAT2 for an injected conversion. The position of the result depends on the basic operating mode (compatibility or enhanced) and on the selected resolution (8-bit or 10-bit). Note: Bitfield CHNR of register ADC_DAT is loaded by the ADC to indicate, which channel the result refers to. Bitfield CHNR of register ADC_DAT2 is loaded by the CPU to select the analog channel, which is to be injected. ADC_DAT ADC Result Register 15 14 13 12 11 10 SFR (FEA0H/50H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CHNR rwh ADRES rwh ADC_DAT2 ADC Chan. Inj. Result Reg. 15 14 13 12 11 10 ESFR (F0A0H/50H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CHNR rw ADRES rwh Field CHNR ADRES Bits Type Function Channel Number (identifies the converted analog channel) A/D Conversion Result The digital result of the most recent conversion. In compatibility mode, the result is placed as follows: 8-bit: ADRES[9:2] 10-bit: ADRES[9:0] In enhanced mode, the result is placed as follows: 8-bit: ADRES[11:4] 10-bit: ADRES[11:2] Note: Unused bits of ADRES are always set to 0. [15:12] rw[h] [11:0] rwh User's Manual ADC_X71, V2.1 16-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.1 Fixed Channel Conversion Modes programming the mode selection bitfield ADM to 00B (continuous conversion). After starting the converter ADBSY will be set and the channel specified in bitfield the conversion is complete, the interrupt request flag These modes are selected by (single conversion) or to 01B through bit ADST the busy flag ADCH will be converted. After ADCIR will be set. In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST. In Continuous Conversion Mode the converter will automatically start a new conversion of the channel specified in ADCH. ADCIR will be set after each completed conversion. When bit ADST is reset by software, while a conversion is in progress, the converter will complete the current conversion and then stop and reset bit ADBSY. User's Manual ADC_X71, V2.1 16-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.2 Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM to 10B (single conversion) or to 11B (continuous conversion). Auto Scan modes automatically convert a sequence of analog channels, beginning with the channel specified in bitfield ADCH and ending with channel 0, without requiring software to change the channel number. After starting the converter through bit ADST, the busy flag ADBSY will be set and the channel specified in bitfield ADCH will be converted. After the conversion is complete, the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the next lower channel. ADCIR will be set after each completed conversion. After conversion of channel 0 the current sequence is complete. In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST. In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH. When bit ADST is reset by software, while a conversion is in progress, the converter will complete the current sequence (including conversion of channel 0) and then stop and reset bit ADBSY. #3 #2 #1 #0 #3 #2 Conversion of Channel.. Write ADC_DAT ADC_DAT Full Generate Interrupt Request Read of ADC_DAT; Result of Channel: #x #3 #2 #1 #0 #3 #x #3 #2 ADC_DAT Full; Channnel 0 # 1 Result Lost #3 Overrun Error Interrupt Request MC_ADC0001_AUTOSCAN Figure 16-3 Auto Scan Conversion Mode Example User's Manual ADC_X71, V2.1 16-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.3 Wait for Read Mode If in default mode of the ADC a previous conversion result has not been read out of the result register by the time a new conversion is complete, the previous result is lost because it is overwritten by the new value, and the A/D overrun error interrupt request flag ADEIR will be set. In order to avoid error interrupts and the loss of conversion results especially when using continuous conversion modes, the ADC can be switched to "Wait for Read Mode" by setting bit ADWR. If the result value has not been read by the time the current conversion is complete, the new result is stored in a temporary buffer and the next conversion is suspended (ADST and ADBSY will remain set in the meantime, but no end-of-conversion interrupt will be generated). After reading the previous value the temporary buffer is copied into ADC_DAT (generating an ADCIR interrupt) and the suspended conversion is started. This mechanism applies to both single and continuous conversion modes. Note: While in standard mode continuous conversions are executed at a fixed rate (determined by the conversion time), in "Wait for Read Mode" there may be delays due to suspended conversions. However, this only affects the conversions, if the CPU (or PEC) cannot keep track with the conversion rate. #3 Conversion of Channel.. #2 #1 wait #0 #3 Write ADC_DAT ADC_DAT Full Temp-Latch Full Generate Interrupt Request Read of ADC_DAT; Result of Channel: #x #3 #2 1 Hold Result in Temp-Latch #1 #0 #3 #x #3 #2 #1 #0 MC_ADC0002_WAITREAD Figure 16-4 Wait for Read Mode Example User's Manual ADC_X71, V2.1 16-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.4 Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel (also while the ADC is running in a continuous or auto scan mode) without changing the current operating mode. After the conversion of this specific channel the ADC continues with the original operating mode. Channel Injection mode is enabled by setting bit ADCIN and requires the Wait for Read Mode (ADWR = 1). The channel to be converted in this mode is specified in bitfield CHNR of register ADC_DAT2. Note: Bitfield CHNR in ADC_DAT2 is not modified by the A/D converter, but only the ADRES bitfield. Since the channel number for an injected conversion is not buffered, bitfield CHNR of ADC_DAT2 must never be modified during the sample phase of an injected conversion, otherwise the input multiplexer will switch to the new channel. It is recommended to only change the channel number with no injected conversion running. #x Conversion of Channel.. # x-1 # x-2 # x-3 # x-4 # ... Write ADC_DAT; # x+1 ADC_DAT Full Read ADC_DAT Injected Conversion of Channel # y ADC_DAT2 Full # x+1 #x #x # x-1 # x-1 # x-2 # x-2 #y Write ADC_DAT2 Int. Request ADEINT # x-3 # x-3 # x-4 # x-4 Channel Injection Request Read ADC_DAT2 MC_ADC0003_INJECT Figure 16-5 Channel Injection Example User's Manual ADC_X71, V2.1 16-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter A Channel Injection can be Triggered in Three Ways: * * * setting of the Channel Injection Request bit ADCRQ via software a compare or a capture event of Capture/Compare register CC31 of the CAPCOM2 unit, which also sets bit ADCRQ. a period-match of timer T13 of the CAPCOM6 unit, which also sets bit ADCRQ. The second method triggers a channel injection at a specific time, on the occurrence of a predefined count value of the CAPCOM2 timers, stored in register CC31. Note: The channel injection request bit ADCRQ will be set on any selected injection trigger (interrupt request of CAPCOM2 channel CC31 or period match of CAPCOM6 timer T13), regardless whether the channel injection mode is enabled or not. It is recommended to always clear bit ADCRQ before enabling the channel injection mode. After the completion of the current conversion (if any is in progress) the converter will start (inject) the conversion of the specified channel. When the conversion of this channel is complete, the result will be placed into the alternate result register ADC_DAT2, and a Channel Injection Complete Interrupt request will be generated, which uses the interrupt request flag ADEIR (for this reason the Wait for Read Mode is required). Note: The result of an injected conversion is directly written to ADC_DAT2. If the previous result has not been read in the meantime, it is overwritten. Standard conversions are suspended if the temporary buffer is full. User's Manual ADC_X71, V2.1 16-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Arbitration of Conversions Conversion requests that are activated while the ADC is idle immediately trigger the respective conversion. If a conversion is requested while another conversion is currently in progress the operation of the A/D converter depends on the kind of the involved conversions (standard or injected). Note: A conversion request is activated if the respective control bit (ADST or ADCRQ) is toggled from 0 to 1, i.e. the bit must have been zero before being set. Table 16-2 summarizes the ADC operation in the possible situations. Table 16-2 Conversion in Progress Standard Conversion Arbitration New Requested Conversion Standard Abort running conversion, and start requested new conversion.1) Complete running conversion, start requested conversion after that. Injected Complete running conversion, start requested conversion after that. Complete running conversion, start requested conversion after that. Bit ADCRQ will be 0 for the second conversion, however. Injected 1) If an injected conversion is pending when a standard conversion is re-started, the injected conversion is executed before the newly started standard conversion. User's Manual ADC_X71, V2.1 16-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.3 Automatic Calibration The ADC of the XC167 features automatic self-calibration. This calibration corrects gain errors, which are mainly due to process variation, and offset errors, which are mainly due to temperature changes. Two types of calibration are supported: * * Reset calibration performs a thorough basic calibration of the ADC after a reset. In particular this is required after a power-on reset. Post-calibration performs one small calibration step after each conversion. Reset Calibration After a reset, a thorough power-up calibration is performed automatically to correct gain and offset errors of the A/D converter. To achieve best calibration results, the reference voltages as well as the supply voltages must be stable during the power-up calibration. During the calibration sequence a series of calibration cycles is executed, where the step width for adjustments is reduced gradually. The total number of executed calibration cycles depends on the actual properties of the respective ADC module. The maximum duration of the power-up calibration is 11,696 cycles of the basic clock fBC. Status flag CAL is set as long as this power-up calibration takes place. Note: The reset calibration must be completed (CAL = 0) before entering Sleep mode, Idle mode, or Powerdown mode. Otherwise, the analog comparator remains active and draws its supply current, which is undesired during power-save conditions. Post-Calibration After each conversion a small calibration step can be executed. For 8-bit and 10-bit conversions post-calibration is not mandatory in order not to exceed the total unadjusted error (TUE) specified in the data sheet. Post-calibration can be disabled by setting bit CALOFF in register ADC_CTR0. When disabled, the post-calibration cycles are skipped which reduces the total conversion time. Note: Calibration may be disabled only after the reset calibration is complete. User's Manual ADC_X71, V2.1 16-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.4 Conversion Timing Control When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next the sampled voltage is converted to a digital value in successive steps, which correspond to the resolution of the ADC. During these phases (except for the sample time) the internal capacitances are repeatedly charged and discharged via pins VAREF and VAGND. The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. The maximum current, however, that a source can deliver, depends on its internal resistance. The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the XC167 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjusting the A/D converter of the XC167 to the properties of the system: Fast Conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High Internal Resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. The conversion rate in this case may be considerably lower, however. Control Bitfields For the timing control of the conversion and the sample phase two mechanisms are provided: * Standard timing control uses two 2-bit fields in register ADC_CON to select prescaler values for the general conversion timing and the duration of the sample phase. This provides compact control, while limiting the prescaler factors to a few steps. Improved timing control uses two 6-bit fields in register ADC_CON1 (compatibility mode) or register ADC_CTR2/ADC_CTR2IN (enhanced mode). This provides a wide range of prescaler factors, so the ADC can be better adjusted to the internal and external system circumstances. * Improved timing control is selected by setting bit ICST in register ADC_CON1 in compatibility mode, or by selecting enhanced mode. User's Manual ADC_X71, V2.1 16-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Standard Timing Control Standard timing control is performed by using two 2-bit fields in register ADC_CON. Bitfield ADCTC (conversion time control) selects the basic conversion clock (fBC), used for the operation of the A/D converter. The sample time is derived from this conversion clock and controlled by bitfield ADSTC. The sample time is always a multiple of 8 fBC periods. Table 16-3 lists the possible combinations. Table 16-3 Standard Conversion and Sample Timing Control A/D Converter Basic Clock fBC1) ADC_CON.13|12 (ADSTC) 00 01 10 11 Sample Time tS ADC_CON.15|14 (ADCTC) 00 01 10 11 fADC/4 fADC/2 fADC/16 fADC/8 tBC x 8 tBC x 16 tBC x 32 tBC x 64 Improved Timing Control To provide a finer resolution for programming of the timing parameters, wider bitfields have been implemented for timing control (the 2-bit bitfields in register ADC_CON are disregarded in all cases). In compatibility mode (with bit ICST = 1), the bitfields in register ADC_CON1 are used for all conversions. In enhanced mode (bit MD = 1), the bitfields in register ADC_CTR2 are used for standard conversions. Injected conversions use the bitfields in register ADC_CTR2IN. Bitfield ADCTC (conversion time control) selects the basic conversion clock (fBC), used for the operation of the A/D converter. The sample time is derived from this conversion clock and controlled by bitfield ADSTC. The sample time is always a multiple of 4 fBC periods. Table 16-4 lists the possible combinations. Table 16-4 ADCTC 00'0000B = 00H 00'0001B = 01H 00'0010B = 02H ... 11'1111B = 3FH Improved Conversion and Sample Timing Control A/D Converter Basic Clock fBC1) ADSTC 00'0000B = 00H 00'0001B = 01H 00'0010B = 02H ... 11'1111B = 3FH Sample Time tS fADC/1 fADC/2 fADC/3 fADC/(ADCTC + 1) fADC/64 tBC x 8 tBC x 12 tBC x 16 tBC x 4 x (ADSTC + 2) tBC x 260 1) The limit values for fBC (see data sheet) must not be exceeded when selecting ADCTC and fADC. User's Manual ADC_X71, V2.1 16-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Total Conversion Time Examples The time for a complete conversion includes the sample time tS, the conversion itself (successive approximation and calibration), and the time required to transfer the digital value to the result register as shown in the example below (standard conversion timing). The timings refer to module clock cycles, where tADC = 1/fADC. * * * * * * * Assumptions: fADC = 40 MHz (i.e. tADC = 25 ns), ADCTC = 01B, ADSTC = 00B Basic clock: fBC = fADC/2 = 20 MHz, i.e. tBC = 50 ns Sample time: tS = tBC x 8 = 400 ns With post-calibr.: tC10P = tS + 52 x tBC + 6 x tADC = (2600 + 400 + 150) ns = 3.15 s Post-calibr. off: tC10 = tS + 40 x tBC + 6 x tADC = (2000 + 400 + 150) ns = 2.55 s With post-calibr.: tC8P = tS + 44 x tBC + 6 x tADC = (2200 + 400 + 150) ns = 2.75 s Post-calibr. off: tC8 = tS + 32 x tBC + 6 x tADC = (1600 + 400 + 150) ns = 2.15 s Conversion 10-bit: Conversion 8-bit: Note: For the exact specification please refer to the data sheet of the selected derivative. User's Manual ADC_X71, V2.1 16-20 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.5 A/D Converter Interrupt Control At the end of each conversion, interrupt request flag ADCIR in interrupt control register ADC_CIC is set. This end-of-conversion interrupt request may cause an interrupt to vector ADCINT, or it may trigger a PEC data transfer which reads the conversion result from register ADC_DAT, e.g. to store it into a table in internal RAM for later evaluation. The interrupt request flag ADEIR in register ADC_EIC will be set either, if a conversion result overwrites a previous value in register ADC_DAT (error interrupt in standard mode), or if the result of an injected conversion has been stored into ADC_DAT2 (endof-injected-conversion interrupt). This interrupt request may be used to cause an interrupt to vector ADEINT, or it may trigger a PEC data transfer. ADC_CIC ADC Conversion Intr. Ctrl. Reg. SFR (FF98H/CCH) 15 14 13 12 11 10 9 8 GPX rw 7 6 5 4 Reset Value: - - 00H 3 2 1 0 ADC ADC IR IE rwh rw ILVL rw GLVL rw ADC_EIC ADC Error Intr. Ctrl. Reg. 15 14 13 12 11 10 SFR (FF9AH/CDH) 9 8 GPX rw 7 6 5 4 Reset Value: - - 00H 3 2 1 0 ADE ADE IR IE rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual ADC_X71, V2.1 16-21 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.6 Interfaces of the ADC Module The ADC is connected to its environment in different ways. Internal Connections The capture/compare signal CC31IO of the CAPCOM2 unit and the timer T13 period match signal of the CAPCOM6 unit are connected to the ADC, providing optional trigger sources for injected conversions. The 2 interrupt request lines of the ADC are connected to the interrupt control block. External Connections The analog input signals for the ADC are connected with Port 5 of the XC167 (input only). Two dedicated pins (VAREF and VAGND) provide the analog reference voltage for the conversion mechanism. User's Manual ADC_X71, V2.1 16-22 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter System Control Unit (SCU) fADC ADCDIS P5.0/AN0 P5.1/AN1 P5.2/AN2 Interrupt Control Block ADC_CIRQ ADC_EIRQ P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 ADC Module Port P5 Control P5.7/AN7 P5.8 P5.9 P5.10/AN10 CAPCOM2 Unit CC31_CIT CAPCOM6 Unit T13_PM P5.11/AN11 P5.12/AN12 P5.13/AN13 VAREF VGND P5.14/AN14 P5.15/AN15 GPT External Inputs MCA05417_X7 Figure 16-6 ADC Module IO Interface User's Manual ADC_X71, V2.1 16-23 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17 Capture/Compare Units The XC167 provides two, almost identical, Capture/Compare (CAPCOM) units, which only differ in the way they are connected to the pins. Each CAPCOM unit provides 16 capture/compare channels, which interact with 2 timers. A CAPCOM channel can capture the contents of a timer on specific internal or external events, or it can compare a timer's contents with given values, and modify output signals in case of a match. Data Registers T0, T0REL T1, T1REL T7, T7REL T8, T8REL CC0-CC3 CC4-CC7 CC8-CC11 CC12-CC15 CC16-CC19 CC20-CC23 CC24-CC27 CC28-CC31 E E CC1_M0 CC1_M1 CC1_M2 CC1_M3 CC2_M4 CC2_M5 CC2_M6 CC2_M7 CC1/2_SEE CC1/2_OUT CC1/2_SEM CC1/2_DRM CC1/2_IOC CC0...15 CC0...15IC CCM0...3 T01CON T0, T1 T0/1REL T0IC, T1IC CC1/2_SEE CC1/2_SEM CC1/2_DRM CC1/2_OUT CC1/2_IOC CAPCOM1 Register 0...15 CAPCOM1 Intr. Ctrl. Reg. 0...15 CAPCOM1 Mode Ctrl. Reg. 0...3 CAPCOM1 Timer Control Reg. CAPCOM1 Timer Register CAPCOM1 Timer Reload Register CAPCOM1 Timer x Intr. Ctrl. Reg. CAPCOM Single Event En. Reg. CAPCOM Single Event Mode Reg. CAPCOM Double Reg. Mode Reg. CAPCOM Output Register CAPCOM Input/Outp. Control Reg. SYSCON3 CC16...31 CC16...31IC CCM4...7 T78CON T7, T8 T7/8REL T7IC, T8IC Px DPx ODPx ALTSEL0Px ALTSEL1Px SYSCON3 E CAPCOM2 Register 16...31 CAPCOM2 Intr. Ctrl. Reg. 16...31 CAPCOM2 Mode Ctrl. Reg. 4...7 CAPCOM2 Timer Control Reg. CAPCOM2 Timer Register CAPCOM2 Timer Reload Register CAPCOM2 Timer x Intr. Ctrl. Reg. Port x Data Register Port x Direction Control Register Port x Open Drain Control Register Port x Alternate Outp. Select Reg.0 Port x Alternate Outp. Select Reg.1 System Ctrl. Reg. 3 (Per. Mgmt.) mc_capcom120100_registers.vsd Control Registers T01CON Interrupt Control T0IC T1IC Port Registers P6, DP6 ODP6 ALTSEL0P6 P7, DP7 ODP7 ALTSEL0/1P7 P9, DP9 ODP9 E E E E ALTSEL0/1P9 P2, DP2 ODP2 ALTSEL0P2 P1L, P1H DP1L, DP1H ALTSEL0P1L/H E E E E E E E E E T78CON T7IC T8IC CC0IC-CC3IC CC4IC-CC7IC CC8IC-CC11IC CC12IC-CC15IC CC16IC-CC19IC CC20IC-CC23IC CC24IC-CC27IC CC28IC-CC31IC Figure 17-1 SFRs Associated with the CAPCOM Units User's Manual CC12_X81, V2.1 17-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units With this mechanism, each CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a minimum of software intervention. From the programmer's point of view, the term `CAPCOM unit' refers to a set of registers which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and their direction control bits (see also Figure 17-1). A CAPCOM unit is typically used to handle high speed IO tasks such as pulse and waveform generation, pulse width modulation, or recording of the time when a specific event occurs. It also supports the implementation of up to 16 software-controlled interrupt events. Each CAPCOM Unit consists of two 16-bit timers (T0/T1, T7/T8), each with its own reload register (TxREL), and a bank of sixteen dual-purpose 16-bit capture/compare registers (CCy). The input clock for the CAPCOM timers is programmable to several prescaled values of the module input clock (fCC), or it can be derived from the overflow/underflow of timer T6. T0/T7 may also operate in counter mode (from an external input), clocked by external events. Each capture/compare register may be programmed individually for capture or compare operation, and each register may be allocated to either of the two timers. Each capture/compare register has one signal associated with it, which serves as an input signal for the capture operation or as an output signal for the compare operation. The capture operation causes the current timer contents to be latched into the respective capture/compare register, triggered by an event (transition) on the associated input signal. This event also activates the associated interrupt request line. The compare operation may cause an output signal transition on the associated output signal, when the allocated timer increments to the value stored in a capture/compare register. The compare match event also activates the associated interrupt request line. In Double-register compare mode a pair of registers controls one common output signal. The compare output signals are available via a dedicated output register, and may also control the output latches of the connected port pins. The output path can be selected. For the switching of the output signals two timing schemes (see Section 17.8) can be selected: In Staggered Mode1) the output signals are switched consecutively in 8 steps, which distributes the switching steps over a certain time. In staggered mode, the maximum resolution is 8 tCC. In Non-Staggered Mode the output signals are switched immediately at the same time. In non-staggered mode, the maximum resolution is 1 tCC. Figure 17-2 shows the basic structure of a CAPCOM unit. 1) Staggered mode is compatible with the CAPCOM units of previous 16-bit controllers. User's Manual CC12_X81, V2.1 17-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Reload Reg. T0REL/T7REL fCC T0IN/T7IN T6OUF CCxIO CCxIO T0/T7 Input Control Timer T0/T7 T0IRQ, T7IRQ CCxIRQ CCxIRQ Mode Control (Capture or Compare) Sixteen 16-bit Capture/ Compare Registers CCxIO CCxIRQ T1/T8 Input Control T1IRQ, T8IRQ fCC T6OUF Timer T1/T8 Reload Reg. T1REL/T8REL CAPCOM1 provides channels x = 0 ... 15, CAPCOM2 provides channels x = 16 ... 31. (see signals CCxIO and CCxIRQ) MCB05418 Figure 17-2 CAPCOM Unit Block Diagram User's Manual CC12_X81, V2.1 17-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.1 The CAPCOM Timers The primary use of the timers T0/T7 and T1/T8 is to provide two independent time bases for the capture/compare channels of each unit. The maximum resolution is 8 tCC in staggered mode, and 1 tCC in non-staggered mode. The basic structure of the two timers, illustrated in Figure 17-3, is identical, except for the input pin (see mark). Reload Reg. TxREL fCC Prescaler fTx TxM MUX TxI T6OUF Count Timer Tx TxIRQ Edge TxIN Select TxI TxR to Capure/Compare Register Array TxI x = 0, 1, 7, 8 MCB05419 Figure 17-3 Block Diagram of a CAPCOM Timer Note: When an external input signal is connected to the input lines of both T0 and T7, these timers count the input signal synchronously. Thus, the two timers can be regarded as one timer whose contents can be compared with 32 compare registers. The functions of the CAPCOM timers are controlled via the bit-addressable control registers T01CON and T78CON. The high-byte of T01CON controls T1, the low-byte of T01CON controls T0. The high-byte of T78CON controls T8, the low-byte of T78CON controls T7. The control options are identical for all four timers (except for external input). In all modes, the timers are always counting upward. The current timer values are accessible for the CPU in the timer registers Tx, which are non bit-addressable registers. When the CPU writes to a register Tx in the state immediately before the respective timer increment or reload is to be performed, the CPU write operation has priority and the increment or reload is disabled to guarantee correct timer operation. User's Manual CC12_X81, V2.1 17-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units CC1_T01CON Timer 0/1 Control Register 15 14 T1R rw 13 12 11 T1M rw 10 SFR (FF50H/A8H) 9 T1I rw 8 7 6 T0R rw 5 4 Reset Value: 0000H 3 T0M rw 2 1 T0I rw 0 CC2_T78CON Timer 7/8 Control Register 15 14 T8R rw 13 12 11 T8M rw 10 SFR (FF20H/90H) 9 T8I rw 8 7 6 T7R rw 5 4 Reset Value: 0000H 3 T7M rw 2 1 T7I rw 0 Field TxR Bits 14, 6 Type rw Description Timer/Counter Tx Run Control 0 Timer/Counter Tx is disabled 1 Timer/Counter Tx is enabled Timer/Counter Tx Mode Selection 0 Timer Mode 1 Counter Mode Timer/Counter Tx Input Selection Timer Mode (TxM = 0): Input frequency fTx = fCC/2( TxM 11, 3 rw TxI [10:8], [2:0] rw The timer run flags TxR allow the starting and stopping of the timers. The following description of the timer modes and operation always applies to the enabled state of the timers, i.e. the respective run flag is assumed to be set. User's Manual CC12_X81, V2.1 17-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer Mode In Timer Mode (TxM = 0), the input clock for a CAPCOM timer is derived from fCC, divided by a programmable prescaler. Each timer has its own individual prescaler, controlled through the individual bitfields TxI in the timer control registers T01CON and T78CON. The input frequency fTx for a timer Tx and its resolution rTx are determined by the following formulas: Staggered Mode: f CC [ MHz ] f Tx [ MHz ] = ------------------------( 2 Non-Staggered Mode: ( (17.1) f CC [ MHz ] f Tx [ MHz ] = ------------------------ 2 2 r Tx [ s ] = ------------------------f CC [ MHz ] (17.2) When a timer overflows from FFFFH to 0000H, it is reloaded with the value stored in its respective reload register TxREL. The reload value determines the period PTx between two consecutive overflows of Tx as follows: Staggered Mode: ( 2 - 16 (17.3) (17.4) After a timer has been started by setting its run flag (TxR), the first increment will occur within the time interval which is defined by the selected timer resolution. All further increments occur exactly after the time defined by the timer resolution. Examples for timer input frequencies, resolution and periods, which result from the selected prescaler option in TxI when using a 40 MHz clock, are listed in Table 17-1 below. The numbers for the timer periods are based on a reload value of 0000H. Note that some numbers may be rounded. User's Manual CC12_X81, V2.1 17-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Table 17-1 TxI Timer Tx Input Clock Selection for Timer Mode, fCC = 40 MHz Prescaler Input Frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.0625 kHz 40 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz Resolution Period Non-Staggered Mode 000B 001B 010B 011B 100B 101B 110B 111B 000B 001B 010B 011B 100B 101B 110B 111B 8 16 32 64 128 256 512 1024 1 2 4 8 16 32 64 128 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 25 ns 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 13.11 ms 26.21 ms 52.43 ms 104.86 ms 209.72 ms 419.43 ms 838.86 ms 1677.72 ms 1.6384 ms 3.2768 ms 6.5536 ms 13.11 ms 26.21 ms 52.43 ms 104.86 ms 209.72 ms Non-Staggered Mode User's Manual CC12_X81, V2.1 17-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Counter Mode In Counter Mode (TxM = 1), the input clock of a CAPCOM timer is either derived from an associated external input pin, T0IN/T7IN, or from the over-/underflows of GPT timer T6. Using an external signal connected to pin TxIN as a counting signal is only possible for timers T0 and T7. The only counter option for timers T1 and T8 is using the over/underflows of the GPT timer T6 (selected by TxI = 000B). Bitfields T0I/T7I are used to select either a positive, a negative, or both a positive and a negative transition of the external signal at pin T0IN/T7IN to trigger an increment of timer T0/T7. Please note that certain criteria must be met for the external signal and the port pin programming for this mode in order to operate properly. These conditions are detailed in Chapter 17.10. Timer Overflow and Reload When a CAPCOM timer contains the value FFFFH at the time a new count trigger occurs, a timer interrupt request is generated, and the timer is loaded with the contents of its associated reload register TxREL. The timer then resumes incrementing with the next count trigger starting from the reloaded value. The reload registers TxREL are not bitaddressable. After reset, they contain the value 0000H. User's Manual CC12_X81, V2.1 17-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.2 CAPCOM Timer Interrupts Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set. This flag can be used to generate an interrupt or trigger a PEC service request, when enabled by the respective interrupt enable bit TxIE. Each timer has its own bitaddressable interrupt control register and its own interrupt vector. The organization of the interrupt control registers TxIC is identical with the other interrupt control registers. CC1_T0IC CAPCOM T0 Intr. Ctrl. Reg. 15 14 13 12 11 10 SFR (FF9CH/CEH) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T0IR T0IE rw rwh rw ILVL rw GLVL rw CC1_T1IC CAPCOM T1 Intr. Ctrl. Reg. 15 14 13 12 11 10 SFR (FF9EH/CFH) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T1IR T1IE rw rwh rw ILVL rw GLVL rw CC2_T7IC CAPCOM T7 Intr. Ctrl. Reg. 15 14 13 12 11 10 ESFR (F17AH/BEH) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T7IR T7IE rw rwh rw ILVL rw GLVL rw CC2_T8IC CAPCOM T8 Intr. Ctrl. Reg. 15 14 13 12 11 10 ESFR (F17CH/BFH) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T8IR T8IE rw rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual CC12_X81, V2.1 17-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.3 Capture/Compare Channels The 16-bit capture/compare registers CC0 through CC15 (CC16 through CC31) are used as data registers for capture or compare operations with respect to timers T0/T7 and T1/T8. The capture/compare registers are not bit-addressable. The functions of the 16 capture/compare registers of a unit are controlled by 4 bitaddressable 16-bit mode control registers, named CC1_M0 ... CC1_M3 (CC2_M4 ... CC2_M7), which are all organized identically (see description below). Each register contains the bits for mode selection and timer allocation for four capture/comp. registers. Capture/Compare Registers for the CAPCOM1 Unit (CC15 ... CC0) CC1_M0 CAPCOM Mode Ctrl. Reg. 0 15 ACC 3 rw 14 13 MOD3 rw 12 11 ACC 2 rw 10 SFR (FF52H/A9H) 9 MOD2 rw 8 7 ACC 1 rw 6 5 MOD1 rw 4 Reset Value: 0000H 3 ACC 0 rw 2 1 MOD0 rw 0 CC1_M1 CAPCOM Mode Ctrl. Reg. 1 15 ACC 7 rw 14 13 MOD7 rw 12 11 ACC 6 rw 10 SFR (FF54H/AAH) 9 MOD6 rw 8 7 ACC 5 rw 6 5 MOD5 rw 4 Reset Value: 0000H 3 ACC 4 rw 2 1 MOD4 rw 0 CC1_M2 CAPCOM Mode Ctrl. Reg. 2 15 ACC 11 rw 14 13 MOD11 rw 12 11 ACC 10 rw 10 SFR (FF56H/ABH) 9 MOD10 rw 8 7 ACC 9 rw 6 5 MOD9 rw 4 Reset Value: 0000H 3 ACC 8 rw 2 1 MOD8 rw 0 CC1_M3 CAPCOM Mode Ctrl. Reg. 3 15 ACC 15 rw 14 13 MOD15 rw 12 11 ACC 14 rw 10 SFR (FF58H/ACH) 9 MOD14 rw 8 7 ACC 13 rw 17-10 6 5 MOD13 rw 4 Reset Value: 0000H 3 ACC 12 rw 2 1 MOD12 rw V2.0, 2004-04 0 User's Manual CC12_X81, V2.1 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Capture/Compare Registers for the CAPCOM2 Unit (CC31 ... CC16) CC2_M4 CAPCOM Mode Ctrl. Reg. 4 15 ACC 19 rw 14 13 MOD19 rw 12 11 ACC 18 rw 10 SFR (FF22H/91H) 9 MOD18 rw 8 7 ACC 17 rw 6 5 MOD17 rw 4 Reset Value: 0000H 3 ACC 16 rw 2 1 MOD16 rw 0 CC2_M5 CAPCOM Mode Ctrl. Reg. 5 15 ACC 23 rw 14 13 MOD23 rw 12 11 ACC 22 rw 10 SFR (FF24H/92H) 9 MOD22 rw 8 7 ACC 21 rw 6 5 MOD21 rw 4 Reset Value: 0000H 3 ACC 20 rw 2 1 MOD20 rw 0 CC2_M6 CAPCOM Mode Ctrl. Reg. 6 15 ACC 27 rw 14 13 MOD27 rw 12 11 ACC 26 rw 10 SFR (FF26H/93H) 9 MOD26 rw 8 7 ACC 25 rw 6 5 MOD25 rw 4 Reset Value: 0000H 3 ACC 24 rw 2 1 MOD24 rw 0 CC2_M7 CAPCOM Mode Ctrl. Reg. 7 15 ACC 31 rw 14 13 MOD31 rw 12 11 ACC 30 rw 10 SFR (FF28H/94H) 9 MOD30 rw 8 7 ACC 29 rw 6 5 MOD29 rw 4 Reset Value: 0000H 3 ACC 28 rw 2 1 MOD28 rw 0 Field ACCy Bits 15, 11, 7, 3 [14:12], [10:8], [6:4], [2:0] Type rw Description Allocation Bit for CAPCOM Register CCy 0 CCy allocated to Timer T0 or T7, respectively 1 CCy allocated to Timer T1 or T8, respectively Mode Selection for CAPCOM Register CCy See Table 17-2. MODy rw User's Manual CC12_X81, V2.1 17-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Each of the registers CCy may be individually programmed for capture mode or for one of 4 different compare modes, and may be allocated individually to one of the two timers of the respective CAPCOM unit. A special double-register compare mode combines two registers to act on one common output signal. When capture or compare operations are disabled for one of the CCy registers, it may be used for general purpose variable storage. Table 17-2 Mode Disabled Selection of Capture Modes and Compare Modes MODy 000 Selected Operating Mode Disable Capture and Compare Modes The respective CAPCOM register may be used for general variable storage. Capture on Positive Transition (Rising Edge) at Pin CCyIO Capture on Negative Transition (Falling Edge) at Pin CCyIO Capture on Positive and Negative Transition (Both Edges) at Pin CCyIO Compare Mode 0: Interrupt Only Several interrupts per timer period. Can enable double-register compare mode for Bank2 registers. Compare Mode 1: Toggle Output Pin on each Match Several compare events per timer period. Can enable double-register compare mode for Bank1 registers. Compare Mode 2: Interrupt Only Only one interrupt per timer period. Compare Mode 3: Set Output Pin on each Match Reset output pin on each timer overflow; only one interrupt per timer period. Capture 001 010 011 Compare 100 101 110 111 The detailed discussion of the capture and compare modes is valid for all the capture/compare channels, so registers, bits and pins are only referenced by a placeholder. Note: A capture or compare event on channel 31 may be used to trigger a channel injection on the XC167's A/D converter if enabled. User's Manual CC12_X81, V2.1 17-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.4 Capture Mode Operation In Capture Mode, the current contents of a CAPCOM timer are latched (captured) into the respective capture/compare register in response to an external event. This is used, for example, to record the time at which an external event has occurred, or to measure the distance between two external events in timer increments. The event to cause a capture of a timer's contents can be programmed to be either the positive, the negative, or both the positive and the negative transition of the external signal connected to the input pin. This triggering transition is selected by bitfield MODy in the respective mode control register. When the selected external signal transition occurs, the selected timer's contents is latched into the capture/compare register and the respective interrupt request line CCyIRQ is activated. This can cause an interrupt or PEC service request, when enabled. Note: A capture input can be used as an additional external interrupt input. The capture operation can be disregarded in this case. Either the contents of timer T0/T7 or T1/T8 can be captured, selected by the timer allocation control bit ACCy in the respective mode control register. Input Clock Interrupt Requests Timer T0/T7 Timer T1/T8 ACCy Edge CCyIO Select MUX CCyIRQ Capture Register CCy MODy MCB05420 Figure 17-4 Capture Mode Block Diagram For capture operation, the respective pin must be programmed for input. To ensure that a transition of the input signal is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 17.10. User's Manual CC12_X81, V2.1 17-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.5 Compare Mode Operation The compare modes allow triggering of events (interrupts and/or output signal transitions) or generation of pulse trains with minimum software overhead. In all compare modes, the 16-bit value stored in a capture/compare register CCy (in the following also referred to as `compare value') is continuously compared with the contents of the allocated timer (T0/T7 or T1/T8). If the current timer contents match the compare value, the interrupt request line associated with register CCy is activated and, depending on the compare mode, an output signal can be generated at the corresponding output pin CCyIO. Four different compare modes are available, which can be selected individually for each of the capture/compare registers by bitfield MODy in the respective mode control register. Modes 0 and 2 do not influence the output signals. In the following, each mode is described in detail. In addition to these `single-register' modes, a `double-register' compare mode enables two registers to operate on the same pin. This feature can further reduce software overhead, as two different compare values can be programmed to control a sequence of transitions for a signal. See Section 17.5.5 for details for this operation. In all Compare Modes, the comparator performs an `equal to' comparison. This means, a match is only detected when the timer contents are equal to the contents of a compare register. In addition, the comparator is only enabled in the clock cycle directly after the timer was incremented by hardware. This is done to prevent repeated matches if the timer does not operate with the highest possible input clock (either in timer or counter mode). In this case, the timer contents would remain at the same value for several or up to thousands of cycles. This operation has the side-effect, that software modifications of the timer contents will have no effect regarding the comparator. If a timer is set by software to the same value stored in one of the compare registers, no match will be detected. If a compare register is set to a value smaller than the current timer contents, no action will take place. For the exact operation of the port output function, please see Section 17.6. When two or more compare registers are programmed to the same compare value1), their corresponding interrupt request flags will be set and the selected output signals will be generated after the allocated timer is incremented to this compare value. Further compare events on the same compare value are disabled2) until the timer is incremented again or written to by software. After a reset, compare events for register CCy will only become enabled, if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register. 1) In staggered mode these interrupts and output signals are generated sequentially (see Section 17.8). 2) Even if more compare cycles are executed before the timer increments (lower timer frequency) a given compare value only results in one single compare event. User's Manual CC12_X81, V2.1 17-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.5.1 Compare Mode 0 This is an interrupt-only mode which can be used for software timing purposes. In this mode, the interrupt request line CCyIRQ is activated each time a match is detected between the contents of the compare register CCy and the allocated timer. A match means, the contents of the timer are equal to (`=') the contents of the compare register. Several of these compare events are possible within a single timer period, if the compare value in register CCy is updated during the timer period. The corresponding port signal CCyIO is not affected by compare events in this mode and can be used as general purpose IO. Note: If compare mode 0 is programmed for one of the bank2 registers the doubleregister compare mode may be enabled for this register (see Chapter 17.5.5). 17.5.2 Compare Mode 1 This is a compare mode which influences the associated output signal. Besides this, the basic operation is as in compare mode 0. Each time a match is detected between the contents of the compare register CCy and the allocated timer, the interrupt request line CCyIRQ is activated. In addition, the associated output signal is toggled. Several of these compare events are possible within a single timer period, if the compare value in register CCy is updated during the timer period. Note: If compare mode 1 is programmed for one of the bank1 registers the doubleregister compare mode may be enabled for this register (see Section 17.5.5). For the exact operation of the port output signal, please see Section 17.6. User's Manual CC12_X81, V2.1 17-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer T0/T7 Timer T1/T8 T1IRQ, T8IRQ T0IRQ, T7IRQ ACCy MUX Mode 1 only! Mode & Output Ctrl. MODy Mode Control Comparator =? to Port Logic CCyIRQ SEEy SEMy Compare Register CCy MCB05421 Figure 17-5 Compare Mode 0 and 1 Block Diagram Note: The signal remains unaffected in compare mode 0. Figure 17-6 illustrates a few example cases for compare modes 0 and 1. In all examples, the reload value of the used timer is set to FFF9H. When the timer overflows, it starts counting from this value upwards. In Case 1, register CCy contains the value FFFCH. When the timer reaches this value, a match is detected, and the interrupt request line CCyIRQ is activated. In compare mode 0, this is all that will happen. In compare mode 1, additionally the associated port output is toggled, causing an inversion of the output signal. If the contents of register CCy are not changed, this operation will take place each time the timer reaches the programmed compare value. In Case 2, software reloads the compare register CCy with FFFFH after the first match with FFFCH has occurred. As the timer continues to count up, it finally reaches this new compare value, and a new match is detected, activating the interrupt request line (both modes) and toggling the output signal (compare mode 1). If then the compare value is left unchanged, the next match will occur when the timer reaches FFFFH again. This example illustrates, that further compare matches are possible within the current timer period (this is in contrast to compare modes 2 and 3). User's Manual CC12_X81, V2.1 17-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer Contents FFFF FFFE FFFD FFFC FFFB FFFA FFF9 Reload Value = FFF9 FFF9 FFFA FFFC FFFB FFFD FFFE FFFF CCxIO Case 1 CC0 = FFFF CCxIO Case 2 CC0 = FFFA CCxIO Case 3 CC0 = FFF9 CCxIO Case 4 Symbolizes activation of the interrupt request line CCyIRQ MCT05422 CC0 = FFFD CC0 = FFFC CC0 = FFFA CC0 = FFFC CC0 = FFFF CC0 = FFFB Figure 17-6 Examples for Compare Modes 0 and 1 In Case 3, a new compare value, higher than the current timer contents, causes a new match within the current timer period. The compare register is reloaded with FFFAH after the first match (at FFFCH). However, the timer has already passed this value. Thus, it will take until the timer reaches FFFAH in the following timer period to cause the desired compare match. Reloading register CCy now with a value higher than the current timer contents will cause the next match within this period. In Case 4, the compare values are equal to the timer reload value or to the maximum count value, FFFFH. User's Manual CC12_X81, V2.1 17-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.5.3 Compare Mode 2 Compare mode 2 is an interrupt-only mode similar to compare mode 0. The main difference is that only one compare match, corresponding to one interrupt request, is possible within a given timer period. When a match is detected in compare mode 2 for the first time within a count period of the allocated timer, the interrupt request line CCyIRQ is activated. In addition, all further compare matches within the current timer period are disabled, even if a new compare value, higher than the current timer contents, would be written to the register. This blocking is only released when the allocated timer overflows. A new compare value written to the compare register after the first match will only go into effect within the following timer period. 17.5.4 Compare Mode 3 Compare mode 3 is based on compare mode 2, but additionally influences the associated port pin. Only one compare event is possible within one timer period. When a match is detected in compare mode 3 for the first time within a count period of the allocated timer, the interrupt request line CCyIRQ is activated, and the associated output signal is set to 1. In addition, all further compare matches within the current timer period are disabled, even if a new compare value, higher than the current timer contents, would be written to the register. This blocking is only released when the allocated timer overflows. A new compare value written to the compare register after the first match will only go into effect within the following timer period. The overflow signal is also used to reset the associated output signal to 0. Special attention has to be paid when the compare value is set equal to the timer reload value. In this case, the compare match signal would try to set the output signal, while the timer overflow tries to reset the output signal. This conflict is avoided such that the state of the output signal is left unchanged in this case. Note: When the compare value is changed from a value above the current timer contents to a value below the current timer contents, the new value is not recognized before the next timer period. For the exact operation of the port output signal, please see Section 17.6. User's Manual CC12_X81, V2.1 17-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units T1IRQ, T8IRQ T0IRQ, T7IRQ Timer T0/T7 Timer T1/T8 MUX ACCy MUX ACCy Mode 3 only! Mode & Output Ctrl. MODy Mode Control Comparator =? to Port Logic CCyIRQ SEEy SEMy Compare Register CCy MCB05423 Figure 17-7 Compare Mode 2 and 3 Block Diagram Note: The port latch and signal remain unaffected in compare mode 2. Figure 17-8 illustrates a few timing examples for compare modes 2 and 3. In all examples, the reload value of the used timer is set to FFF9H. When the timer overflows, it starts counting from this value upwards. In Case 1, register CCy contains the value FFFCH. When the timer reaches this value, a match is detected, and the interrupt request line CCyIRQ is activated. In compare mode 2, this is all that will happen. In compare mode 3, additionally the associated port output is set to 1. The timer continues to count, and finally reaches its overflow. At this point, the port output is reset to 0 again. Note that, although not shown in the diagrams, the overflow signal of the timer also activates the associated interrupt request line TxIRQ. If the contents of register CCy are not changed, the port output will be set again during the following timer period, and reset again when the timer overflows. This operation is ideal for the generation of a pulse width modulated (PWM) signal with a minimum of software overhead. The pulse width is varied by changing the compare value accordingly. In Case 2, the compare operation is blocked after the first match within a timer period. After the first match at FFFCH, the interrupt request is generated and the port output is set. In addition, further compare matches are disabled. If now a new compare value is written to register CCy, no interrupt request and no port output influence will take place, although the new compare value is higher than the current timer contents. Only after the overflow of the timer, the compare logic is enabled again, and the next match will be User's Manual CC12_X81, V2.1 17-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units detected at FFFFH. One can see, that this operation is ideal for PWM generation, as software can write a new compare value regardless of whether this value is higher or lower than the current timer contents. It is assured that the new value (usually written to the compare register in the appropriate interrupt service routine) will only go into effect during the following timer period. Timer Contents FFFF FFFE FFFD FFFC FFFB FFFA FFF9 Reload Value = FFF9 FFF9 FFFA FFFC FFFB FFFD FFFE FFFF CCxIO Case 1 CC0 = FFFF CCxIO Case 2 CC0 = FFFA CCxIO Case 3 CC0 = FFFA CCxIO Case 4 MCT05424 CC0 = FFFC CC0 = FFFC Figure 17-8 Timing Example for Compare Modes 2 and 3 Note: In compare mode 2, only interrupt requests are generated, in mode 3, also the output signals are generated. In Case 3, further examples for the operation of the compare match blocking are illustrated. In Case 4, a new compare value is written to a compare register before the first match within the timer period. One can see that, of course, the originally programmed compare match (at FFFAH) will not take place. The first match will be detected at FFFCH. However, it is important to note that the reprogramming of the compare register took place asynchronously - this means, the register was written to without any regard to the current contents of the timer. This is dangerous in the sense that the effect of such an asynchronous reprogramming is not easily predictable. If the timer would have already reached the originally programmed compare value of FFFAH by the time the software User's Manual CC12_X81, V2.1 17-20 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units wrote to the register, a match would have been detected and the reprogramming would go into effect during the next timer period. The examples in Figure 17-9 show special cases for compare modes 2 and 3. Case 1 illustrates the effect when the compare value is equal to the reload value of the timer. An interrupt is generated in both modes. In mode 3, the output signal is not affected - it remains at the high level. Setting the compare value equal to the reload value easily enables a 100% duty cycle signal for PWM generation. The important advantage here is that the compare interrupt is still generated and can be used to reload the next compare value. Thus, no special treatment is required for this case (see Case 3). Cases 2, 4, and 5 show different options for the generation of a 0% duty cycle signal. Case 2 shows an asynchronous reprogramming of the compare value equal to the reload value. At the end of the current timer period, a compare interrupt will be generated, which enables software to set the next compare value. The disadvantage of this method is that at least two timer periods will pass until a new regular compare value can go into effect. The compare match with the reload value FFF9H will block further compare matches during that timer period. This is additionally illustrated by Case 4. Timer Contents FFFF FFFE FFFD FFFC FFFB FFFA FFF9 Reload Value = FFF9 Int. CCxIO Case 1 Int. CCxIO Case 2 Int. CCxIO Case 3 Int. CCxIO Case 4 Int. CCxIO Case 5 CC0 = FFF8 CC0 = FFF9 Int. CC0 = FFFC No Comp. CC0 = FFF9 Int. CC0 = FFF9 Int. CC0 = FFF9 Int. Int. FFF9 FFFA FFFC FFFB FFFD FFFE FFFF CC0 = FFFB CC0 = FFFC Int. MCT05425 Figure 17-9 Special Cases in Compare Modes 2 and 3 User's Manual CC12_X81, V2.1 17-21 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Case 5 shows an option to get around this problem. Here, the compare register is reloaded with FFF8H, a value which is lower than the timer reload value. Thus, the timer will never reach this value, and no compare match will be detected. The output signal will be set to 0 after the first timer overflow. However, after the second overflow, software now reloads the compare register with a regular compare value. As no compare blocking has taken place (since there was no compare match), the newly written compare value will go into effect during the current timer period. 17.5.5 Double-Register Compare Mode The Double-Register Compare Mode makes it possible to further reduce software overhead for a number of applications. In this mode, two compare registers work together to control one output. This mode is selected via the DRM register, or by a special combination of compare modes for the two registers. For double-register compare mode, the 16 capture/compare registers of a CAPCOM unit are regarded as two banks of 8 registers each. The lower eight registers form bank1, while the upper eight registers form bank2. For double-register mode, a bank1 register and a bank2 register form a register pair. Both registers of this register pair operate on the pin associated with the bank1 register. The relationship between the bank1 and bank2 register of a pair and the effected output pins for double-register compare mode is listed in Table 17-3. Table 17-3 Register Pairs for Double-Register Compare Mode CAPCOM1 Unit Register Pair Bank 1 CC0 CC1 CC2 CC3 CC4 CC5 CC6 CC7 Bank 2 CC8 CC9 CC10 CC11 CC12 CC13 CC14 CC15 Used Output Pin CC0IO CC1IO CC2IO CC3IO CC4IO CC5IO CC6IO CC7IO CAPCOM2 Unit Register Pair Control Bitfield in Bank 1 Bank 2 CC1DRM DR0M DR1M DR2M DR3M DR4M DR5M DR6M DR7M CC16 CC17 CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31 Used Output Pin CC16IO CC17IO CC18IO CC19IO CC20IO CC21IO CC22IO CC23IO Control Bitfield in CC2DRM DR0M DR1M DR2M DR3M DR4M DR5M DR6M DR7M The double-register compare mode can be programmed individually for each register pair. Double-register compare mode can be selected via a certain combination of compare modes for the two registers of a pair. The bank1 register must be programmed User's Manual CC12_X81, V2.1 17-22 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units for mode 1 (with port influence), while the bank2 register must be programmed for mode 0 (interrupt-only). Double-register compare mode can be controlled (this means, enabled or disabled) for each register pair via the associated control bitfield DRxM in register CC1_DRM or CC2_DRM, respectively. CC1_DRM Double-Reg. Cmp. Mode Reg. 15 14 13 12 11 10 SFR (FF5AH/ADH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DR7M rw DR6M rw DR5M rw DR4M rw DR3M rw DR2M rw DR1M rw DR0M rw CC2_DRM Double-Reg. Cmp. Mode Reg. 15 14 13 12 11 10 SFR (FF2AH/95H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DR7M rw DR6M rw DR5M rw DR4M rw DR3M rw DR2M rw DR1M rw DR0M rw Field DRxM Bits [1:0], [3:2], [5:4], [7:6], [9:8], [11:10], [13:12], [15:14] Type rw Description Double Register x Compare Mode Selection 00 DRM is controlled via the combination of compare modes 1 and 0 (compatibility mode) 01 DRM disabled regardless of compare modes 10 DRM enabled regardless of compare modes 11 Reserved Note: "x" indicates the register pair index in a bank. Double-register compare mode can be controlled individually for each of the register pairs. In the block diagram of the double-register compare mode (Figure 17-10), a bank2 register will be referred to as CCz, while the corresponding bank1 register will be referred to as CCy. User's Manual CC12_X81, V2.1 17-23 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer T0/T7 Timer T1/T8 MUX ACCy MUX ACCz DRyM MODy Mode Control Comp. =? Mode & Output Ctrl. Comparator =? CCyIRQ SEEy SEMy to Port Logic DRyM MODz Mode Control CCzIRQ SEEz SEMz Compare Register CCy Compare Register CCz z=y+8 MCB05426 Figure 17-10 Double-Register Compare Mode Block Diagram When a match is detected for one of the two registers in a register pair (CCy or CCz), the associated interrupt request line (CCyIRQ or CCzIRQ) is activated, and pin CCyIO, corresponding to the bank1 register CCy, is toggled. The generated interrupt always corresponds to the register that caused the match. Note: If a match occurs simultaneously for both register CCy and register CCz of the register pair, pin CCyIO will be toggled only once, but two separate compare interrupt requests will be generated. Each of the two registers of a pair can be individually allocated to one of the two timers in the CAPCOM unit. This offers a wide variety of applications, as the two timers can run in different modes with different resolution and frequency. However, this might require sophisticated software algorithms to handle the different timer periods. Note: The signals CCzIO (which do not serve for double-register compare mode) may be used for general purpose IO. User's Manual CC12_X81, V2.1 17-24 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.6 Compare Output Signal Generation This section discusses the interaction between the CAPCOM Unit and the Port Logic. The block diagram illustrated in Figure 17-11 details the logic of the block "Mode & Output Control", shown in Figure 17-5, Figure 17-7, and Figure 17-10. Each output signal is latched in its associated bit of the respective output latch register CCx_OUT. The individual bits are updated each time an associated compare event occurs. The bits of these registers are connected to the respective port pins as an alternate output function of a port line. Compare signals can also directly affect the associated port output latch Px. In this case, the port latch must be selected for the respective pin. The direct port latch option is disabled in non-staggered mode or it can be disabled by setting bit PL in register CCx_IOC. Register CCx_OUT is always updated in parallel to the update of the port output latch. CC1_OUT Compare Output Reg. 15 CC 15 IO rwh 14 CC 14 IO rwh 13 CC 13 IO rwh 12 CC 12 IO rwh 11 CC 11 IO rwh 10 SFR (FF5CH/AEH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 10 IO IO IO IO IO IO IO IO IO IO IO rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh CC2_OUT Compare Output Reg. 15 CC 15 IO rwh 14 CC 14 IO rwh 13 CC 13 IO rwh 12 CC 12 IO rwh 11 CC 11 IO rwh 10 SFR (FF2CH/96H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 10 IO IO IO IO IO IO IO IO IO IO IO rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field CCyIO Bits Type Description Compare Output for Channel y Alternative port output for the associated port pin. 15 ... 0 rwh User's Manual CC12_X81, V2.1 17-25 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units STAG PL Compare Match TxOV Output Value Control _ >1 & Port Latch 0 OUT Latch 1 MUX Driver Port Pin Pm.n MODy ALTSEL0Pn Direction CAPCOM Logic Port Logic MCB05427 Figure 17-11 Port Output Block Diagram for Compare Modes Note: A compare output signal is visible at the pin only in compare modes 1 or 3. The output signal of a compare event can either be a 1, a 0, the complement of the current level, or the previous level. The block `Output Value Control' determines the correct new level based on the compare event, the timer overflow signal, and the current states of the Port and OUT latches. For the output toggle function (e.g. in compare mode 1), the state of the output latch is read, inverted, and then written back. The associated output pins either drives the port latch signal or the OUT signal, selected by register ALTSEL (see Figure 17-11). Note: If the port output latch is written to by software at the same time it would be altered by a compare event, the software write will have priority. In this case the hardwaretriggered change will not become effective. User's Manual CC12_X81, V2.1 17-26 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.7 Single Event Operation If an application requires that one and only one compare event needs to take place (within a certain time frame), single event operation helps to reduce software overhead and to eliminate the need for fast reaction upon events. In order to achieve a single event operation without this feature, software would have to either disable the compare mode or write a new value, which is outside of the count range of the timer, into the compare register, after the programmed compare match has taken place. Thus, usually an interrupt service routine is required to perform this operation. Interrupt response time may be critical if the timer period is very short - the disable operation needs to be completed before the timer would reach the same value again. The single event operation eliminates the need for software to react after the first compare match. The complete operation can be set up before the event, and no action is required after the event. The hardware takes care of generating only one event, and then disabling all further compare matches. This option is programmed via the Single Event Mode register CCx_SEM and the Single Event Enable register CCx_SEE. Each register provides one bit for each CCy register of a unit. CC1_SEM Single Event Mode Ctrl. Reg. 15 14 13 12 11 10 SFR (FE28H/14H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw CC2_SEM Single Event Mode Ctrl. Reg. 15 14 13 12 11 10 SFR (FE2CH/16H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field SEMy Bits 15 ... 0 Type rw Description Single Event Mode Control 0 Single Event Mode disabled for channel y 1 Single Event Mode enabled for channel y User's Manual CC12_X81, V2.1 17-27 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units CC1_SEE Single Event Enable Reg. 15 14 13 12 11 10 SFR (FE2EH/17H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh CC2_SEE Single Event Enable Reg. 15 14 13 12 11 10 SFR (FE2AH/15H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field SEEy Bits 15 ... 0 Type rw Description Single Event Enable Control 0 Single Event disabled for channel y 1 Single Event enabled for channel y Note: This bit is cleared by hardware after the event. To setup a single event operation for a CCy register, software first programs the desired compare operation and compare value, and then sets the respective bit in register CCx_SEM to enable the single event mode. At last, the respective event enable bit in register CCx_SEE is set. When the programmed compare match occurs, all operations of the selected compare mode take place. In addition, hardware automatically disables all further compare matches and reset the event enable bit in register CCx_SEE to 0. As long as this bit is cleared, any compare operation is disabled. To setup a new event, this bit must first be set again. User's Manual CC12_X81, V2.1 17-28 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.8 Staggered and Non-Staggered Operation The CAPCOM units can run in one of two basic operation modes: Staggered Mode and Non-Staggered Mode. The selection between these modes is performed via register IOC. CC1_IOC I/O Control Register 15 14 13 12 11 10 - ESFR (F062H/31H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 ST AG rw 1 PL rw 0 - CC2_IOC I/O Control Register 15 14 13 12 11 10 - ESFR (F066H/33H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 ST AG rw 1 PL rw 0 - Field STAG Bits 2 Type rw Description Staggered Mode Control 0 CAPCOM operates in Staggered Mode 1 CAPCOM operates in Non-Staggered Mode Port Lock Control 0 Compare output signals affect the associated port output latch 1 Direct influence of the port output latch by the compare output signals is disabled PL 1 rw Note: Whenever Non-Staggered Mode is enabled (STAG = 1) or Port Lock is activated (PL = 1), the port output registers are not changed by the CAPCOM unit. In staggered mode, a CAPCOM operation cycle consists of 8 module clock cycles, and the outputs of the compare events of the different registers are staggered, that is, the outputs for compare matches with the same compare value are not switched at the same time, but with a fixed time delay. This operation helps to reduce noise and peak power consumption caused by simultaneous switching outputs. In non-staggered Mode, a CAPCOM operation cycle is equal to one module clock cycle, and all compare outputs for compare events with the same compare value are switched User's Manual CC12_X81, V2.1 17-29 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units in the same clock cycle. This mode offers a faster operation and increased resolution of the CAPCOM unit, 8 times higher than in staggered mode. Staggered Mode Figure 17-12 illustrates the staggered mode operation. In this example, all CCy registers are programmed for compare mode 3. Registers CC0, CC1, and CC2 are all programmed for a compare value of FFFEH. When the timer increments to FFFEH, the comparator detects a match for all of the three registers. The output CC0IO of register CC0 is switched to 1 one cycle after the comparator match. However, the outputs CC1IO and CC2IO are not switched at the same time, but one, respectively two cycles later. This staggering of the outputs continues for all registers including register CC7. The number of the register indicates the delay of the output signal in clock cycles - the output of register CC7 is switched 7 cycles later than the one of register CC0. In the example, the compare value for register CC7 is set to FFFDH. Thus, the output is switched in the last clock cycle of the CAPCOM cycle in which the timer reached FFFDH. When the timer overflows, all compare outputs are reset to 0 (compare mode 3). Again, the staggering of the output signals can be seen from Figure 17-12. Looking at registers CC8 through CC15 shows that their outputs are switched in parallel to the respective outputs of registers CC0 through CC15. In fact, the staggering is performed in parallel for the upper and the lower register bank. In this way, it is assured, that both compare signals of a register pair in double-register compare mode operate simultaneously. In staggered mode direct port latch switching (see Section 17.6) is possible. However, it is possible to use the alternate output function option of the associated port pins to output the compare signals. User's Manual CC12_X81, V2.1 17-30 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer contents = FFFD Timer increments to FFFE Timer increments to FFFF Timer overflow Timer is reloaded with FFFC 1 CAPCOM Cycle = 8 fCC Clock Cycles CC0 = FFFE CC1 = FFFE CC2 = FFFE CC3 = FFFF CC4 = FFFE CC5 = FFFF CC6 = FFFF CC7 = FFFD CC8 = FFFE CC9 = FFFE CC10 = FFFE CC11 = FFFF CC12 = FFFE CC13 = FFFF CC14 = FFFF CC15 = FFFD 1 CAPCOM Cycle = 8 fCC Clock Cycles MCT05428 Figure 17-12 Staggered Mode Operation User's Manual CC12_X81, V2.1 17-31 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Non-Staggered Mode To gain maximum speed and resolution with the CAPCOM unit, it can be switched to non-staggered mode. In this mode, one CAPCOM operation cycle is equal to one module clock cycle. Timer increment and the comparison of its new contents with the contents of the compare register takes place within one clock cycle. The appropriate output signals are switched in the following clock cycle (in parallel to the next possible timer increment and comparison). Figure 17-13 illustrates the non-staggered mode. Note that when the timer overflows, it also takes one additional clock cycle to switch the output signals. Note: In non-staggered mode, direct port latch switching is disabled. User's Manual CC12_X81, V2.1 17-32 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer contents = FFFD Timer increments to FFFE Timer increments to FFFF Timer overflow Timer is reloaded with FFFC 1 CAPCOM Cycle = 1 fCC Clock Cycle CC0 = FFFE CC1 = FFFE CC2 = FFFE CC3 = FFFF CC4 = FFFE CC5 = FFFF CC6 = FFFF CC7 = FFFD CC8 = FFFE CC9 = FFFE CC10 = FFFE CC11 = FFFF CC12 = FFFE CC13 = FFFF CC14 = FFFF CC15 = FFFD 1 CAPCOM Cycle = 1 fCC Clock Cycle MCT05429 Figure 17-13 Non-Staggered Mode Operation User's Manual CC12_X81, V2.1 17-33 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.9 CAPCOM Interrupts Upon a capture or compare event, the interrupt request flag CCxIR for the respective capture/compare register CCx is automatically set. This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCxIE. Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred. Each of the capture/compare registers has its own bitaddressable interrupt control register and its own interrupt vector allocated. These registers are organized in the same way as all other interrupt control registers. The basic register layout is shown below, Table 17-4 lists the associated addresses. CCx_CCyIC CAPCOM Intr. Ctrl. Reg. 15 14 13 12 11 10 (E)SFR (Table 17-4) 9 8 GPX rw 7 6 5 4 Reset Value: - - 00H 3 2 1 0 CCy CCy IR IE rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual CC12_X81, V2.1 17-34 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Table 17-4 CAPCOM Unit Interrupt Control Register Addresses CAPCOM1 Unit Register Name CC1_CC0IC CC1_CC1IC CC1_CC2IC CC1_CC3IC CC1_CC4IC CC1_CC5IC CC1_CC6IC CC1_CC7IC CC1_CC8IC CC1_CC9IC CC1_CC10IC CC1_CC11IC CC1_CC12IC CC1_CC13IC CC1_CC14IC CC1_CC15IC Address FF78H/BCH FF7AH/BDH FF7CH/BEH FF7EH/BFH FF80H/C0H FF82H/C1H FF84H/C2H FF86H/C3H FF88H/C4H FF8AH/C5H FF8CH/C6H FF8EH/C7H FF90H/C8H FF92H/C9H FF94H/CAH FF96H/CBH Reg. Space SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR CAPCOM2 Unit Register Name CC2_CC16IC CC2_CC17IC CC2_CC18IC CC2_CC19IC CC2_CC20IC CC2_CC21IC CC2_CC22IC CC2_CC23IC CC2_CC24IC CC2_CC25IC CC2_CC26IC CC2_CC27IC CC2_CC28IC CC2_CC29IC CC2_CC30IC CC2_CC31IC Address F160H/B0H F162H/B1H F164H/B2H F166H/B3H F168H/B4H F16AH/B5H F16CH/B6H F16EH/B7H F170H/B8H F172H/B9H F174H/BAH F176H/BBH F178H/BCH F184H/C2H F18CH/C6H F194H/CAH Reg. Space ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR User's Manual CC12_X81, V2.1 17-35 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.10 External Input Signal Requirements The external input signals of a CAPCOM unit are sampled by the CAPCOM logic based on the module clock and the basic operation mode (staggered or non-staggered mode). To assure that a signal level is recognized correctly, its high or low level must be held active for at least one complete sampling period. The duration of a sampling period is one module clock cycle in non-staggered mode, and 8 module clock cycles in staggered mode. To recognize a signal transition, the signal needs to be sampled twice. If the level of the first sampling is different to the level detected during the second sampling, a transition is recognized. Therefore, a minimum of two sampling periods are required for the sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than half the module clock frequency in non-staggered mode, and a 1/16th of the module clock frequency in staggered mode. Table 17-5 summarizes the requirements and limits for external input signals. Table 17-5 CAPCOM External Input Signal Limits Non-Staggered Mode Maximum Input Frequency Staggered Mode fCC/2 fCC/16 8/fCC Minimum Input Signal Level 1/fCC Duration In order to use an external signal as a count or capture input, the port pin to which it is connected must be configured as input. Note: For example for test purposes a pin used as a count or capture input may be configured as output. Software or an other peripheral may control the respective signal and thus trigger count or capture events. In order to cause a compare output signal to be seen by the external world, the associated port pin must be configured as output. Compare output signals can either directly switch the port latch, or the output of the CCx_OUT latch is used as an alternate output function of a port. User's Manual CC12_X81, V2.1 17-36 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.11 Interfaces of the CAPCOM Units The CAPCOM units CAPCOM1 (see Figure 17-14) and CAPCOM2 (see Figure 17-15) are connected to their environment in different ways. Internal Connections The overflow/underflow signal T6OUF of GPT2 timer T6 is connected to the CAPCOM units, providing an optional clock source for the CAPCOM timers. The 18 interrupt request lines of each CAPCOM unit are connected to the interrupt control block. Note: The input lines from Port 2, connected with the CAPCOM1 unit, can also be used as individual external interrupt inputs. External Connections The capture/compare signals of both CAPCOM units are connected with input/output ports of the XC167. Depending on the selected direction, these ports may provide capture trigger signals from the external system or issue compare output signals to external circuitry. Note: Capture trigger signals may also be derived from output pins. In this case, software can generate the trigger edges, for example. Timers T0 and T7 can be clocked by an external signal. CAPCOM2's timer input signal T7IN shares a port pin with CAPCOM1's input/output pin CC15IO (see Figure 17-15). Operations in both CAPCOM units can so be combined: * * the CAPCOM1 compare output can be used to clock CAPCOM2 timer T7, or the CAPCOM2 count input signal can be recorded by a CAPCOM1 capture function. User's Manual CC12_X81, V2.1 17-37 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units System Control Unit (SCU) fCC CC1DIS CC0IO CC1IO CC2IO P6.0/CC0IO P6.1/CC1IO P6.2/CC2IO Port P6 Control P6.3/CC3IO P6.4/CC4IO P6.5/CC5IO P6.6/CC6IO P6.7/CC7IO GPT12 Unit T6OUF CC3IO CC4IO T0IRQ T1IRQ CC0IRQ CC1IRQ CC2IRQ CC3IRQ CC4IRQ CC5IRQ CC6IRQ Interrupt Control CC7IRQ CC8IRQ CC9IRQ CC10IRQ CC11IRQ CC12IRQ CC13IRQ CC14IRQ CC15IRQ CAPCOM1 Module CC5IO CC6IO CC7IO CC8IO CC9IO CC10IO CC11IO CC12IO CC13IO CC14IO CC15IO Port P2 Control P2.8/CC8IO P2.9/CC9IO P2.10/CC10IO P2.11/CC11IO P2.12/CC12IO P2.13/CC13IO P2.14/CC14IO P2.15/T7IN/ CC15IO Port P3 Control T0IN P3.0/T0IN External Interrupt Inputs EXnIN Alternate External Interrupt Input MCA05430 Alternate Input Select Figure 17-14 CAPCOM1 Unit Interfaces User's Manual CC12_X81, V2.1 17-38 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units System Control Unit (SCU) fCC CC2DIS CC16IO CC17IO CC18IO Port P9 Control P9.0/CC16IO P9.1/CC17IO P9.2/CC18IO P9.3/CC19IO P9.4/CC20IO P9.5/CC21IO P1L.7/CC22IO P1H.0/CC23IO Port P1 Control P1H.4/CC24IO P1H.5/CC25IO P1H.6/CC26IO P1H.7/CC27IO P7.4/CC28IO Port P7 Control P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO GPT12 Unit T6OUF CC19IO CC20IO T7IRQ T8IRQ CC16IRQ CC17IRQ CC18IRQ CC19IRQ CC20IRQ CC21IRQ CC22IRQ Interrupt Control CC23IRQ CC24IRQ CC25IRQ CC26IRQ CC27IRQ CC28IRQ CC29IRQ CC30IRQ CC31IRQ ADC Injection Trigger CAPCOM2 Module CC21IO CC22IO CC23IO CC24IO CC25IO CC26IO CC27IO CC28IO CC29IO CC30IO CC31IO T7IN Port P2 Control P2.15/T7IN/ CC15IO MCA05431 Figure 17-15 CAPCOM2 Unit Interfaces User's Manual CC12_X81, V2.1 17-39 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18 Capture/Compare Unit 6 (CAPCOM6) The CAPCOM6 unit is made up of a Timer T12 Block with three capture/compare channels and a Timer T13 Block with one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or they can jointly generate control signal patterns to drive AC-motors or inverters. Special operating modes support the control of Brushless DC-motors using Hall sensors or Back-EMF detection. Furthermore, block commutation and control mechanisms for multi-phase machines are supported. Data Registers T12 T12PR T12DTC CC60R CC60SR CC61R CC61SR CC62R CC62SR T13 T13PR CC63R CC63SR X X X X X X X X X X X X X TRPCTR PSLR IS ISS/ISR IEN INP T12IC/T13IC CCU6_IC CCU6_EIC P1L/P1H DP1L/DP1H ALTSEL0P1x SYSCON3 Trap Control Register Passive State Level Register Interrupt Status Register Interrupt Status Set/Reset Register Interrupt Enable Register Interrupt Node Pointer Register CAPCOM6 Timer Interrupt Control Reg. CAPCOM6 Interrupt Control Register CAPCOM6 Error Interrupt Control Reg. PORT1 Data Register PORT1 Direction Control Register PORT1 Alternate Outp. Select Reg. 0 System Control Reg. 3 (Per. Mgmt.) mc_capcom60100_registers.vsd Control Registers CMPSTAT CMPMODIF TCTR0 TCTR2 TCTR4 MODCTR TRPCTR PSLR MCMOUTS MCMOUT MCMCTR T12MSEL X X X X X X X X X X X X Interrupt Control CCU6_IS CCU6_ISS CCU6_ISR CCU6_INP CCU6_IEN X X X X X System Registers P1L DP1L ALTSEL0P1L E E P1H DP1H E E CCU6_T12IC CCU6_T13IC CCU6_EIC CCU6_IC E E E E ALTSEL0P1H SYSCON3 E T12/T13 CAPCOM6 Timer T12/T13 Register T12PR/T13PR CAPCOM6 T12/T13 Period Register T12DTC CAPCOM6 T12 Deadtime Control Reg. TCTRx CAPCOM6 Timer Control Register T12MSEL T12 Capture/Compare Mode Select Reg. CC6xR CAPCOM6 Capture/Compare Register CC6xSR CAPCOM6 Capt./Comp. Shadow Reg. CMPSTAT Capture/Compare State Register CMPMODIF Capture/Comp. State Modification Reg. MODCTR Modulation Control Register MCMOUT Multi-Channel Mode Output Register MCMOUTS Multi-Ch. Mode Output Shadow Reg. MCMCTR Multi-Channel Mode Control Register Figure 18-1 SFRs Associated with the CAPCOM6 Unit User's Manual CAPCOM6_X, V2.0 18-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation of interrupt request signals provide means for efficient software-control. Timer 12 Block Features * * * * * * * * * Three capture/compare channels, each channel can be used either as capture or as compare channel Generation of a three-phase PWM supported (six outputs, individual signals for highside and lowside switches) 16-bit resolution, maximum count frequency = peripheral clock Dead-time control for each channel to avoid short-circuits in the power stage Concurrent update of the required T12/T13 registers Center-aligned and edge-aligned PWM can be generated Single-shot mode supported Many interrupt request sources Hysteresis-like control mode Timer 13 Block Features * * * * * One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock Can be synchronized to T12 Interrupt generation at period-match and compare-match Single-shot mode supported Additional Features * * * * * * * * Block commutation for Brushless DC-drives implemented Position detection via Hall-sensor pattern Hall-Effect noise filter Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage User's Manual CAPCOM6_X, V2.0 18-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Module Kemel Compare Address Decoder Channel 0 T12 Channel 1 Channel 2 Clock Control Start T13 Interrupt Control Channel 3 Compare 1 1 1 1 DeadTime Control Multichannel Control Trap Control Output Select Output Select 3 3+3 2 2 2 Trap Input 1 Capture Input / Output Control CCPOS0 CCPOS1 Hall Input CCPOS2 Compare COUT61 Compare COUT63 COUT60 COUT62 Compare Port Control MCB05506 Figure 18-2 CAPCOM6 Block Diagram The Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. The Timer T13 can work in compare mode only. The multichannel control unit generates output patterns which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. User's Manual CAPCOM6_X, V2.0 18-3 CTRAP T12HR T13RH CC60 CC61 CC62 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.1 Timer T12 Block The timer T12 block is the main unit to generate the 3-phase PWM. A 16-bit counter is connected to 3 channel registers via comparators, which generate a signal when the counter contents match one of the channel register contents. A variety of control functions facilitate the adaptation of the T12 structure to different application needs. Besides the 3-phase PWM generation, the T12 block offers options for individual compare and capture functions, as well as dead-time control and hysteresis-like compare mode. State Bits Capture/Compare Channel 60 Timer T12 Logic Capture/Compare Channel 61 Capture/Compare Channel 62 Ext. Inputs CC60ST To Dead-Time Control and Output Modulation CC61ST CC62ST Input and Control/Status Logic MCA05507 Figure 18-3 Overview Diagram of the Timer T12 Block Figure 18-4 shows a detailed block diagram of Timer T12. It receives its input clock, fT12, from the module clock fCC6 via a programmable prescaler and an optional 1/256 divider. These options are controlled via bitfields T12CLK and T12PRE (see Table 18-1). T12 can count up or down, depending on the selected operation mode. A direction flag, CDIR, indicates the current counting direction. Via a comparator, T12 is connected to a Period Register, T12PR. This register determines the maximum count value for T12. In Edge-Aligned mode, T12 is reset to 0000H after it has reached the period value. In Center-Aligned mode, the count direction of T12 is set from `up' to `down' after it has reached the period value (please note that in this mode, T12 exceeds the period value by one before counting down). In both cases, signal T12_PM (T12 Period Match) is generated. The Period Register receives a new period value from its Shadow Period Register, T12PS, which is loaded via software. The transfer of a new period value from the shadow register into T12PR (see Section 18.8) is controlled via the `T12 Shadow Transfer' control signal, T12_ST. The generation of this signal depends on the operating mode and on control bit STE12. Providing a shadow register for the period value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters. User's Manual CAPCOM6_X, V2.0 18-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Two further signals indicate whether the counter contents are equal to 0000H (T12_ZM) or 0001H (T12_OM). These signals control the counting and switching behavior of T12. The basic operating mode of T12, either Edge-Aligned mode (Figure 18-5) or CenterAligned mode (Figure 18-6), is selected via bit CTM. A Single-Shot control bit, T12SSC, enables an automatic stop of the timer when the current counting period is finished (see Figure 18-7 and Figure 18-8). T12STR T12RR T12STD CTM T12RS T12R fCC6 n 256 MUX fT12 Counter Register T12 T12 Control & Status CDIR STE12 T12RES T12SSC T12CLK T12PRE = 0000H = 0001H Comp. =? T12_ZM T12_OM T12_PM T12_SSEP Read-Only Period Register T12PR T12_ST Write-Only Period Shadow Register T12PR MCA05508 Figure 18-4 Timer T12 Logic and Period Comparators The start or stop of T12 is controlled by the Run bit, T12R. This control bit can be set by software via the associated set/reset bits T12RS or T12RR, or it is reset by hardware according to preselected conditions. Timer T12 can be cleared via control bit T12RES. Setting this write-only bit does only clear the timer contents, but has no further effects, for example, it does not stop the timer. The generation of the T12 shadow transfer control signal, T12_ST, is enabled via bit STE12. This bit can be set or reset by software indirectly through its associated set/reset control bits T12STR and T12STD. Note: The control registers to select the T12 operating mode are described in Section 18.3. User's Manual CAPCOM6_X, V2.0 18-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register T12 represents the counting value of Timer T12. It can only be written while Timer T12 is stopped. Write actions while T12 is running are not taken into account. Register T12 can always be read by software. CCU6_T12 Timer T12 Count Register 15 14 13 12 11 10 XSFR (E890H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T12CV rwh Field T12CV Bits [15:0] Type rwh Description T12 Count Value Represents the 16-bit count value of Timer T12 Register T12PR contains the period value for Timer T12. The period value is compared to the actual count value of T12 and the resulting actions depend on the defined counting rules. CCU6_T12PR Timer T12 Period Register 15 14 13 12 11 10 XSFR (E892H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T12PV rwh Field T12PV Bits [15:0] Type rwh Description T12 Period Value When T12 equals value T12PV a period-match is triggered. When reaching this value, Timer T12 is set to zero (edge-aligned mode) or changes its count direction to down counting (center-aligned mode). This register has a shadow register (using the same address) and the shadow transfer is controlled by bit STE12. A read action by SW delivers the value which is currently used for the period compare, whereas a write action targets the shadow register. The shadow register structure allows concurrent updating of all T12-related values. User's Manual CAPCOM6_X, V2.0 18-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.1.1 Timer T12 Operation The input clock fT12 of Timer T12 is derived from the module clock fCC6 through a programmable prescaler and an optional 1/256 divider. The resulting prescale factors are listed in Table 18-1. The prescaler of T12 is reset while T12 is not running to ensure reproducible timings and delays. Table 18-1 T12CLK 000B 001B 010B 011B 100B 101B 110B 111B Timer T12 Input Clock Options Resulting Input Clock Prescaler Off (T12PRE = 0) Resulting Input Clock Prescaler On (T12PRE = 1) fCC6 fCC6/2 fCC6/4 fCC6/8 fCC6/16 fCC6/32 fCC6/64 fCC6/128 fCC6/256 fCC6/512 fCC6/1024 fCC6/2048 fCC6/4096 fCC6/8192 fCC6/16384 fCC6/32768 The period of the timer is determined by the value in the period Register T12PR and by the timer mode. In Edge-Aligned mode, the timer period is: T12PER = While Timer T12 is running, write accesses to the count register T12 are not taken into account. If T12 is stopped and the Dead-Time counters are 0, write actions to register T12 are immediately taken into account. User's Manual CAPCOM6_X, V2.0 18-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) As described above, T12 can operate in Edge-Aligned mode or Center-Aligned mode. In both modes, a certain set of `counting rules' determine the behavior of the T12 counter. The counting rules lead to a behavior in Edge-Aligned mode as illustrated in Figure 18-5. In the Center-Aligned mode (T12 counts up and down), the counting rules lead to the behavior shown in Figure 18-6. T12 in Edge-Aligned Mode: * With the next clock of fT12 the counter is reset to zero when a Period-Match is detected. The counting direction is always upwards (CDIR = 0). fT12 Period Value T12 Count Period Zero Match Match Zero Up CDIR CC6x Value n+1 Value n+2 Up Shadow Transfer MCT05509 Figure 18-5 T12 Operation in Edge-Aligned Mode User's Manual CAPCOM6_X, V2.0 18-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) T12 in Center-Aligned mode: * * * With the next clock of fT12 the count direction is set to counting up (CDIR = 0) when the counter reaches 0001H while counting down. With the next clock of fT12 the count direction is set to counting down (CDIR = 1) when the Period-Match is detected while counting up. With the next clock of fT12 the counter counts up while CDIR = 0 and it counts down while CDIR = 1. Note: Bit CDIR changes with the next timer clock after the one-match or the periodmatch. Therefore, the timer continues counting in the previous direction for one cycle before actually changing its direction (see Figure 18-6). fT12 Period Value T12 Count Zero Match Period Match Period Match Zero Down CDIR CC6x Value n Value n+1 Value n+1 Value n+2 Up Up Down Shadow Transfer Shadow Transfer MCT05510 Figure 18-6 T12 Operation in Center-Aligned Mode User's Manual CAPCOM6_X, V2.0 18-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) T12 Shadow Transfer Signal, T12_ST A special shadow transfer signal (T12_ST) can be generated to facilitate updating the period and compare values synchronously to the operation of T12. The generation of this signal is requested by software via bit STE12 (set by writing 1 to the write-only bit T12STR, cleared by writing 1 to the write-only bit T12STD). If requested (STE12 = 1), signal T12_ST is generated when: * * * a Period-Match is detected while counting up, or the counter reaches 0001H while counting down, or timer T12 is not running (T12R = 0) When signal T12_ST is active, a shadow register transfer is triggered with the next cycle of the T12 clock. A new period value is loaded from the shadow register into the actual period register T12PR, and new compare values are transferred from their shadow registers into the actual compare registers (see Section 18.1.2). With the shadow register transfer bit STE12 is automatically cleared. T12 Start/Stop and Reset Control Timer T12 is counting while bit T12R is set. Software can control the timer's count operation via bit T12R (set by writing 1 to the write-only bit T12RS, cleared by writing 1 to the write-only bit T12RR). T12R can also be cleared by hardware in Single Shot mode. Software can clear timer T12 by writing 1 to the write-only bit T12RES. This operation only sets the timer contents to 0000H. No further actions will take place, for example, the timer run bit is not cleared. User's Manual CAPCOM6_X, V2.0 18-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Single-Shot Mode The run bit T12R is also influenced by hardware in Single-Shot mode. This mode is enabled through bit T12SSC. When this bit is set, the timer will stop when the current timer period is finished. In Edge-Aligned mode, this is when the timer is cleared to 0000H after having reached the period value. In Center-Aligned mode, the period is finished when the timer has counted down to 0000H. See Figure 18-7 and Figure 18-8. fT12 Compare-Match T12 Count Period Value Compare Value Zero CC6xST T12SSC MCT05511 Figure 18-7 Single-Shot Operation in Edge-Aligned Mode fT12 Compare-Match T12 Count Compare-Match Period Value Compare Value Zero CC6xST T12SSC MCT05512 Figure 18-8 Single-Shot Operation in Center-Aligned Mode User's Manual CAPCOM6_X, V2.0 18-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.1.2 T12 Compare Modes Associated with Timer T12 are three individual capture/compare channels, which can perform compare or capture operations with regard to the contents of the T12 counter. The capture functions are explained in Section 18.1.4. In Compare Mode (see Figure 18-9), the three channels can operate either independently as individual channels, or generate a three-phase PWM pattern. fT12 Counter Register T12 CDIR & CM_61_DN & CM_61_UP Compare Match CM_61 Comp. =? Comp. =? Comp. =? Compare Match CM_62 Compare Match CM_60 Compare Register CC60R Compare Register CC61R Compare Register CC62R T12_ST Compare Shadow Register CC60SR Compare Shadow Register CC61SR Compare Shadow Register CC62SR MCA05513 Figure 18-9 T12 Channel Comparators Each channel is connected to the T12 counter register via its individual equal-to comparator, which generates a match signal when the contents of the counter matches the contents of the associated compare register. Each channel consists of the comparator and a double register structure - the actual compare register CC6xR, feeding the comparator, and an associated shadow register CC6xSR, which is preloaded by software and transferred into the compare register when signal T12 shadow transfer, T12_ST, gets active. Providing a shadow register for the compare value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters (see also Section 18.8). User's Manual CAPCOM6_X, V2.0 18-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Associated with each channel is a State Bit, CC6xST, which holds the status of the compare (or capture) operation (see Figure 18-10). Rising Edge Falling Edge T12R CM_60 Set/Reset Control Logic CDIR Compare State Bit CC60ST CC60ST Change MCC60S/R MSEL60 Rising Edge Falling Edge To Interrupt Control CC60ST CC60ST DTC0_IN To Interrupt Control CC61ST CC61ST DTC1_IN To Interrupt Control CC62ST CC62ST DTC2_IN MCB05514 CM_61 Set/Reset Control Logic Compare State Bit CC61ST CC61ST Change MCC61S/R MSEL61 Rising Edge Falling Edge CM_62 T12_ZM T12_SSEP Set/Reset Control Logic Compare State Bit CC62ST CC62ST Change MCC62S/R MSEL62 Figure 18-10 Compare State Bits Block Diagram for Compare Mode The inputs to the set/reset logic for the CC6xST bits are the timer direction (CDIR), the timer run bit (T12R), the timer zero-match signal (T12_ZM), the end-of-single-shot mode signal (T12_SSEP), and the actual individual compare-match signals CM_6x as well as the mode control bits, MSEL6x. In addition, each state bit can be set or reset by software via the appropriate set and reset bits, MCC6xS and MCC6xR. Note: In Hall Sensor mode, additional inputs are taken into account (see Section 18.5). User's Manual CAPCOM6_X, V2.0 18-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) A hardware-modification of a State Bit CC6xST is only possible while Timer T12 is running (T12R = 1). If this is the case, the following rules apply for setting and resetting the State Bits in Compare Mode (illustrated in Figure 18-11 and Figure 18-12): A State Bit CC6xST is set to 1 * * with the next T12 clock (fT12) after a compare-match when T12 is counting up (i.e., when the counter is incremented above the compare value); with the next T12 clock (fT12) after a zero-match AND a parallel compare-match when T12 is counting up. with the next T12 clock (fT12) after a compare-match when T12 is counting down (i.e., when the counter is decremented below the compare value); with the next T12 clock (fT12) after a zero-match AND NO parallel compare-match when T12 is counting up. A State Bit CC6xST is reset to 0 * * fT12 Compare-Match T12 Count Compare-Match Period Value Compare Value Zero CC6xST MCT05515 Figure 18-11 Compare Operation, Edge-Aligned Mode fT12 Compare-Match T12 Count Compare-Match Period Value Compare Value Zero CC6xST MCT05516 Figure 18-12 Compare Operation, Center-Aligned Mode User's Manual CAPCOM6_X, V2.0 18-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Figure 18-13 illustrates some more examples for compare waveforms. It is important to note that in these examples, it is assumed that some of the compare values are changed while the timer is running. This change is performed via a software preload of the Shadow Register, CC6xSR. The value is transferred to the actual Compare Register CC6xR with the T12 Shadow Transfer signal, T12_ST, which is assumed to be enabled. fT12 Period Value = 5 T12 Count Zero Down CDIR CC6x Value n CC6x = 2 a) CC6x = 1 b) CC6x = 3 c) CC6x = 4 d) CC6x = 5 e) CC6x = 3 f) MCT05517 Up Down Up Value n+1 CC6x = 2 CC6x = 0 CC6x = 3 CC6x = 4 CC6x = 5 CC6x = 6 Value n+2 CC6x = 1 CC6x = 0 CC6x = 3 CC6x = 4 CC6x = 5 CC6x = 6 Value n+3 CC6x = 1 CC6x = 0 CC6x = 3 CC6x = 4 CC6x = 5 CC6x = 6 Figure 18-13 Compare Waveform Examples Example b) illustrates the transition to a duty cycle of 100%. First, a compare value of 0001H is used, then changed to 0000H. Please note that a low pulse with the length of one T12 clock is still produced in the cycle where the new value 0000H is in effect; this pulse originates from the previous value 0001H. In the following timer cycles, the State Bit CCxST remains at 1, producing a 100% duty cycle signal. In this case, the compare rule `zero-match AND compare-match' is in effect. User's Manual CAPCOM6_X, V2.0 18-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Example f) shows the transition to a duty cycle of 0%. The new compare value is set to Period Value CC60R CC62R T12 Count CC61R Zero Down Down CDIR Shadow Transfer CC60ST CC61ST CC62ST Up Down Up MCT05518 Figure 18-14 Three-Channel Compare Waveforms User's Manual CAPCOM6_X, V2.0 18-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Compare Mode Output Path Figure 18-15 gives an overview on the signal path from a channel State Bit to its output pin in its simplest form. As illustrated, a user has a variety of controls to determine the desired output signal switching behavior in relation to the current state of the State Bit, CC6xST. Please refer to Chapter 18.7 for details on the output modulation. State Selection CC6xPS CC6xST State Bit CC6xST DTCx_IN CC6xST & DTRx COUT6xPS Dead-Time Generation CC6xST & DTRx Output Modulation T12 MODENx PSLx Level Select Level Select T12 PSLy MODENy MCA05519 CC6x_O CC6x To Output Pins COUT6x_O COUT6x Figure 18-15 Compare Mode Simplified Output Path Diagram User's Manual CAPCOM6_X, V2.0 18-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Compare Mode Registers In compare mode, registers CC6xR (x = 0, 1, 2) are the actual compare registers for T12. The values stored in CC6xR are compared (all three channels in parallel) to the count value of T12. Registers CC6xR can only be read by SW, the modification of the value is done by a shadow register transfer from the corresponding shadow registers CC6xSR. These registers can be read and written by SW. In capture mode, the current value of the T12 counter register is captured into registers CC6xR or CC6xSR when the corresponding capture event is detected (depending on the selected mode). CCU6_CC60R Channel 0 Capt./Comp. Reg. 15 14 13 12 11 10 XSFR (E898H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC60V rh CCU6_CC61R Channel 1 Capt./Comp. Reg. 15 14 13 12 11 10 XSFR (E89AH/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC61V rh CCU6_CC62R Channel 2 Capt./Comp. Reg. 15 14 13 12 11 10 XSFR (E89CH/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC62V rh Field CC6xV (x = 0, 1, 2) Bits [15:0] Type rh Description Channel x Compare Value In compare mode, the bitfields CC6xV contain the values that are compared to the T12 count value. In capture mode, the captured value of T12 can be read from these registers. User's Manual CAPCOM6_X, V2.0 18-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) CCU6_CC60SR Ch. 0 Capt./Cmp. Shadow Reg. XSFR (E8A0H/--) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC60S rwh CCU6_CC61SR Ch. 1 Capt./Cmp. Shadow Reg. XSFR (E8A2H/--) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC61S rwh CCU6_CC62SR Ch. 2 Capt./Cmp. Shadow Reg. XSFR (E8A4H/--) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC62S rwh Field CC6xS (x = 0, 1, 2) Bits [15:0] Type rwh Description Shadow Register for Channel x Compare Value In compare mode, the contents of bitfields CC6xS are transferred to bitfields CC6xV in registers CC6xR during a shadow transfer. In capture mode, the captured value of T12 can be read from these registers. User's Manual CAPCOM6_X, V2.0 18-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register T12MSEL contains control bits to select the capture/compare functionality of the three channels of Timer T12. CCU6_T12MSEL T12 Mode Select Register 15 14 13 12 11 10 XSFR (E8C6H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 MSEL62 rw MSEL61 rw MSEL60 rw Field MSEL62 MSEL61 MSEL60 Bits [11:8] [7:4] [3:0] Type rw Description Capture/Compare Mode Selection These bitfields select the operating mode of the three T12 capture/compare channels. Each channel (x = 0, 1, 2) can be programmed individually for one of these modes (except for Hall Sensor Mode). See Table 18-2. Table 18-2 MSEL6x 0000B 0001B 0010B 0011B 01XXB 1000B 1001B 101XB 11XXB Capture/Compare Modes Overview Selected Operating Mode Compare outputs disabled, pins CC6x and COUT6x can be used for IO. Compare output on pin CC6x, pin COUT6x can be used for IO. Compare output on pin COUT6x, pin CC6x can be used for IO. Compare output on pins COUT6x and CC6x. Double-Register Capture modes, see Chapter 18.1.4 and Table 18-3. Hall Sensor Mode, see Chapter 18.5. In order to properly enable this mode, all three MSEL6x fields have to be programmed to Hall Sensor mode. Hysteresis-like mode, see Chapter 18.1.5. Multi-Input Capture modes, see Chapter 18.1.4 and Table 18-4. Note: Channel status information is available through the channel state (modification) registers, described in Section 18.3. User's Manual CAPCOM6_X, V2.0 18-20 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.1.3 Dead-Time Generation The generation of (complementary) signals for the highside and the lowside switches of one power inverter phase is based on the same compare channel. For example, if the highside switch should be active while the T12 counter value is above the compare value (State Bit = 1), then the lowside switch should be active while the counter value is below the compare value (State Bit = 0). In most cases, the switching behavior of the connected power switches is not symmetrical concerning the switch-on and switch-off times. A general problem arises if the time for switch-on is smaller than the time for switch-off of the power device. In this case, a short-circuit can occur in the inverter bridge leg, which may damage the complete system. In order to solve this problem by HW, this capture/compare unit contains a programmable Dead-Time Generation Block, which is able to delay the passive to active edge of the switching signals (the active to passive edge is not delayed). The Dead-Time Generation Block, illustrated in Figure 18-16, is built in a similar way for all three channels of T12. Any change of a CC6xST bit triggers the corresponding DeadTime Counter, a single-shot 6-bit down counter which is clocked with the same input clock as T12 (fT12). A trigger pulse DTCx_IN, activated by the change of the State Bit CC6xST, leads to a reload of the dead-time counter with the value DTM stored in register T12DTC and starts the counter. Reload Value DTM DTC0_IN DTE0 & DTC1_IN DTE1 & DTC2_IN DTE2 & 6-bit Down Counter 6-bit Down Counter 6-bit Down Counter DTR2 fT12 DTRES DTR1 DTR0 MCB05520 Figure 18-16 Dead-Time Generation Block Diagram User's Manual CAPCOM6_X, V2.0 18-21 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) While counting down, the output line DTRx is 0. Thus, the reload value determines the length of the low phase (the passive state) of the output signal, and therefore the delay of the 0-to-1 transition of the State Bit outputs. The active state of the output signal is represented by a 1. The programmable reload value DTM applies to all three channels. When the counter reaches zero, the counter is stopped and output line DTRx is set to 1. While DTRx is 0 both outputs are forced into passive state. While DTRx is 1 the outputs can go to active state. Each of the three dead-time counters has its individual enable control bit, DTEx, for the trigger input, DTCx_IN. A reload of a counter is only possible while the counter is not running. This avoids a possible retriggering of the dead-time if a change in the State Bit CC6xST is detected. Figure 18-17 illustrates the waveforms of the dead-time generation (passive state = 0). The associated registers are detailed below. T12 Count Compare CC6xST CC6xST DTCx_IN Down Counter DTRx CC6xST & DTRx CC6xST & DTRx MCT05521 Figure 18-17 Dead-Time Generation Waveforms User's Manual CAPCOM6_X, V2.0 18-22 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register T12DTC controls the dead-time generation for the T12 compare channels. Each channel can be independently enabled/disabled for dead-time generation. If enabled, the transition from passive state to active state is delayed by the value defined by bitfield DTM. CCU6_T12DTC T12 Dead-Time Control Reg. 15 14 13 12 11 10 XSFR (E894H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DTR DTR DTR 2 1 0 rh rh rh DTE DTE DTE 2 1 0 rw rw rw DTM rw Field DTR2 DTR1 DTR0 Bits 14 13 12 Type rh Description Dead Time Run Indication Flags Indicate the status of the dead-time generation for each corresponding compare channel (0, 1, 2) 0 The dead-time counter is stopped 1 The dead-time counter is running (delay is active) Dead-Time Generation Enable Bits Enable/disable the dead-time generation for each corresponding compare channel (0, 1, 2) 0 Dead-time generation is disabled 1 Dead-time generation is enabled Dead-Time Value DTM specifies the programmable delay between switching from the passive state to the active state of the selected outputs DTE2 DTE1 DTE0 10 9 8 rw DTM [5:0] rw Note: The Dead-Time Counters can be cleared by setting bit DTRES in register TCTR4. User's Manual CAPCOM6_X, V2.0 18-23 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.1.4 T12 Capture Modes Each of the three channels of the T12 Block can also be used to capture T12 time information in response to an external signal. There are a number of different modes for capture operation. In all modes, both of the registers of a channel are used. This can reduce the interrupt rate to the CPU, as it needs to react only to every second event. The selection of the capture modes is done via the MSEL6x bitfields in register T12MSEL and can be selected individually for each of the channels. Table 18-3 MSEL6x 0100B 0101B 0110B 0111B 1 2 3 4 Capture Modes Overview Mode Pin CC6x CC6x CC6x CC6x CC6x Active Edge Rising Falling Rising Falling Any CC6nSR Stored in T12 Stored in - - CC6xR CC6xR CC6xR CC6xR CC6xSR CC6xSR CC6xSR CC6xSR Figure 18-18 illustrates Capture Mode 1. When a rising edge (0-to-1 transition) is detected at the corresponding input pin CC6x, the current contents of Timer T12 are captured into register CC6xR. When a falling edge (1-to-0 transition) is detected at pin CC6x, the contents of Timer T12 are captured into register CC6xSR. fT12 Counter Register T12 MSEL6x CC6x Edge MSEL6x Rising Select Falling Detect Set State Bit CC6xST Register CC6xR Shadow Register CC6xSR To Interrupt Logic MCB05522 Figure 18-18 Capture Mode 1 Block Diagram User's Manual CAPCOM6_X, V2.0 18-24 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Capture Modes 2, 3 and 4 are shown in Figure 18-19. They differ only in the active edge causing the capture operation. In each of the three modes, when the selected edge is detected at the corresponding input pin CC6x, the current contents of the shadow register CC6xSR are latched into register CC6xR, and the current Timer T12 contents are captured in register CC6xSR (simultaneous transfer). The active edge is a rising edge at pin CC6x for Capture Mode 2, a falling edge for Mode 3, and both, a rising or a falling edge for Capture Mode 4, as shown in Table 18-3. These capture modes are very useful in cases where there is little time between two consecutive edges of the input signal. fT12 Counter Register T12 MSEL6x CC6x Edge MSEL6x Select Detect Shadow Register CC6xSR Set State Bit CC6xST Register CC6xR Rising Falling To Interrupt Logic MCB05523 Figure 18-19 Capture Modes 2, 3 and 4 Block Diagram User's Manual CAPCOM6_X, V2.0 18-25 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Five further capture modes are called Multi-Input Modes, as they use two different external inputs, pin CC6x and pin CC6POSx. fT12 MSEL6x CC6x Edge Counter Register T12 MSEL6x Select Detect Set State Bit CC6xST Set Rising Falling CC6POSx Edge Register CC6xR Shadow Register CC6xSR To Interrupt Logic Select Detect MSEL6x MSEL6x MCB05524 Figure 18-20 Multi-Input Capture Modes Block Diagram In each of these modes, the current T12 contents are latched in register CC6xR in response to a selected event at pin CC6x, and in register CC6xSR in response to a selected event at pin CC6POSx. The possible events can be opposite input transitions, or the same transitions, or any transition at the two input pins. The different options are detailed in Table 18-4. In each of the various capture modes, the Channel State Bit, CC6xST, is set to 1 when the selected capture trigger event at pin CC6x or CC6POSx has occurred. The State Bit must be reset by software. In addition, appropriate signal lines to the interrupt logic are activated, which can generate an interrupt request to the CPU. Regardless of the selected active edge, all edges detected at pin CC6x lead to the activation of the appropriate interrupt request line (see also Section 18.9). User's Manual CAPCOM6_X, V2.0 18-26 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Table 18-4 MSEL6x 1010B 1011B 1100B 1101B 1110B 1111B Multi-Input Capture Modes Overview Mode 5 6 7 8 9 - Pin CC6x CCPOSx CC6x CCPOSx CC6x CCPOSx CC6x CCPOSx CC6x CCPOSx Active Edge Rising Falling Falling Rising Rising Rising Falling Falling Any Any T12 Stored in CC6xR CC6xSR CC6xR CC6xSR CC6xR CC6xSR CC6xR CC6xSR CC6xR CC6xSR reserved (no capture or compare action) User's Manual CAPCOM6_X, V2.0 18-27 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.1.5 Hysteresis-Like Control Mode The hysteresis-like control mode (MSEL6x = 1001B) offers the possibility to switch off the PWM output if the input CCPOSx becomes 0 by resetting bit CC6xST. This can be used as a simple motor control feature by using a comparator indicating, e.g., overcurrent. While CCPOSx = 0, the PWM outputs of the corresponding channel are driving their passive levels. The setting of bit CC6xST is only possible while CCPOSx = 1. CC6POSx Edge T12R CDIR Detect CM_6x T12_ZM T12_SSEP Set/ Reset Control Logic Bit CC6xST + Dead-Time Generation State Select Logic CC6xO COUT6xO MCC6xS/R MSELx2 MCA05525 Figure 18-21 Hysteresis-Like Control Mode Logic In this mode, the State Bit CC6xST is reset when pin CC6POSx shows a negative edge. As long as input CC6POSx is 0, the outputs of the State Bit are in passive state. When CC6POSx is at high level, the outputs can be in active state and are determined by bit CC6xST (see Figure 18-10 for the state bit logic and Figure 18-15 for the output paths). This mode can be used to introduce a timing-related behavior to a hysteresis controller. A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result. Depending on the operating conditions, the switching frequency and the duty cycle are not fixed, but change permanently. If (outer) time-related control loops based on a hysteresis controller (inner loop) should be implemented, the outer loops show a better behavior if they are synchronized to the inner loops. Therefore, the hysteresis-like mode can be used, which combines timerrelated switching with a hysteresis controller behavior. For example, in this mode, an output can be switched on according to a fixed time base, but it is switched off as soon as a falling edge is detected at input CCPOSx. This mode can be used for standard PWM with overcurrent protection. As long as there is no low level signal at pin CC6POSx, the output signals are generated in the normal manner as described in the previous sections. Only if input CC6POSx shows a low level, e.g. due to the detection of overcurrent, the outputs are shut off to avoid harmful stress to the system. User's Manual CAPCOM6_X, V2.0 18-28 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.2 Timer T13 Block Timer T13 is implemented similarly to Timer T12, but only with one channel in compare mode. A 16-bit up-counter is connected to a channel register via a comparator, which generates a signal when the counter contents match the contents of the channel register. A variety of control functions facilitate the adaptation of the T13 structure to different application needs. In addition, T13 can be triggered synchronously to timer T12 events. State Bit Timer T13 Logic Compare Channel 63 CC63ST To Output Modulation Control/Status Logic MCA05526 Figure 18-22 Overview Diagram of the Timer T13 Block Figure 18-23 shows a detailed block diagram of Timer T13. It receives its input clock, fT13, from the module clock fCC6 via a programmable prescaler and an optional 1/256 divider. T13 can only count up (similar to the Edge-Aligned mode of T12). Via a comparator, T13 is connected to a Period Register, T13PR. This register determines the maximum count value for T13. When T13 reaches the period value, signal T13_PM (T13 Period Match) is generated and T13 is reset to 0000H with the next T13 clock edge. The Period Register receives a new period value from its Shadow Period Register, T13PS, which is loaded via software. The transfer of a new period value from the shadow register into T13PR is controlled via the `T13 Shadow Transfer' control signal, T13_ST. The generation of this signal depends on the associated control bit STE13. Providing a shadow register for the period value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters (see also Section 18.8). Another signal indicates whether the counter contents are equal to 0000H (T13_ZM). A Single-Shot control bit, T13SSC, enables an automatic stop of the timer when the current counting period is finished (see Figure 18-25). User's Manual CAPCOM6_X, V2.0 18-29 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) T13STR T13TEC T13RR T13STD T13TED T13RS fCC6 n 256 MUX fT13 T13R Counter Register T13 T13 Control & Status STE13 T13RES T13SSC T13CLK T13PRE = 0000H Comp. =? T13_ZM T13_PM T13_ST Read-Only Period Register T13PR Write-Only Period Shadow Register T13PS MCA05527 Figure 18-23 T13 Counter Logic and Period Comparators The start or stop of T13 is controlled by the Run bit, T13R. This control bit can be set by software via the associated set/reset bits T13RS or T13RR, or it is reset by hardware according to preselected conditions. Timer T13 can be cleared to 0000H via control bit T13RES. Setting this write-only bit only clears the timer contents, but has no further effects, e.g., it does not stop the timer. The generation of the T13 shadow transfer control signal, T13_ST, is enabled via bit STE13. This bit can be set or reset by software indirectly through its associated set/reset control bits T13STR and T13STD. Two bitfields, T13TEC and T13TED, control the synchronization of T13 to Timer T12 events. T13TEC selects the trigger event, while T13TED determines for which T12 count direction the trigger should be active. Note: The T13 Period Register and its associated shadow register are located at the same physical address. A write access to this address targets the Shadow Register, while a read access reads from the actual period register. User's Manual CAPCOM6_X, V2.0 18-30 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register T13 represents the counting value of Timer T13. It can only be written while Timer T13 is stopped. Write actions while T13 is running are not taken into account. Register T13 can always be read by SW. CCU6_T13 Timer T13 Count Register 15 14 13 12 11 10 XSFR (E8B0H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T13CV rwh Field T13CV Bits [15:0] Type rwh Description Timer T13 Count Value Represents the 16-bit count value of Timer T13 Register T13PR contains the period value for Timer T13. The period value is compared to the actual count value of T13 and T13 is reset when the two values match. This register has a shadow register and the shadow transfer is controlled by bit STE13. A read action by SW delivers the value which is currently used for the period compare, whereas a write action targets the shadow register. The shadow register structure allows a concurrent update of all T13-related values. CCU6_T13PR Timer T13 Period Register 15 14 13 12 11 10 XSFR (E8B2H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T13PV rwh Field T13PV Bits [15:0] Type rwh Description T13 Period Value T13PV defines the count value for T13 which leads to a Period-Match. When reaching this value, Timer T13 is set to zero. User's Manual CAPCOM6_X, V2.0 18-31 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.2.1 T13 Operation The input clock fT13 of Timer T13 is derived from the module clock fCC6 through a programmable prescaler and an optional 1/256 divider. The resulting prescale factors are listed in Table 18-5. The prescaler of T13 is reset while T13 is not running to ensure reproducible timings and delays. Table 18-5 T13CLK 000B 001B 010B 011B 100B 101B 110B 111B Timer T13 Input Clock Options Resulting Input Clock Prescaler Off (T13PRE = 0) Resulting Input Clock Prescaler On (T13PRE = 1) fCC6/1 fCC6/2 fCC6/4 fCC6/8 fCC6/16 fCC6/32 fCC6/64 fCC6/128 fCC6/256 fCC6/512 fCC6/1024 fCC6/2048 fCC6/4096 fCC6/8192 fCC6/16384 fCC6/32768 The period of the timer is determined by the value in the period Register T13PR according to the following formula: T13PER = While Timer T13 is running, write accesses to the count register T13 are not taken into account. If T13 is stopped, write actions to register T13 are immediately taken into account. As described above, T13 can only count up, comparable to the Edge-Aligned mode of T12. This leads to very simple `counting rules' for the T13 counter: * The counter is reset to zero with the next T13 clock edge if a Period-Match is detected. The counting direction is always upwards. The behavior of T13 is illustrated in Figure 18-24. User's Manual CAPCOM6_X, V2.0 18-32 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) fT13 Period Value T13 Count Period Zero Match Match Zero CC63 Value n+1 Value n+2 Shadow Transfer MCT05528 Figure 18-24 T13 Operation T13 Shadow Transfer Signal, T13_ST A special shadow transfer signal (T13_ST) can be generated to facilitate updating the period and compare values synchronously to the operation of T13. The generation of this signal is requested by software via bit STE13 (set by writing 1 to the write-only bit T13STR, cleared by writing 1 to the write-only bit T13STD). If requested (STE13 = 1), signal T13_ST is generated when: * * the counter is reset to 0000H after the Period-Match, or timer T13 is not running (T13R = 0) With signal T13_ST, a new period value is loaded from the shadow register into the actual period register T13PR, and a new compare value is transferred from its shadow register into the actual compare register (see Section 18.1.2). T13 Start/Stop and Reset Control Timer T13 is started through software by setting the write-only bit T13RS. This operation sets the timer run bit T13R, and the timer starts counting. To stop the timer, the writeonly bit T13RR needs to be set to 1. The run bit T13R is cleared to 0, and the timer stops counting. The run bit can also be cleared by hardware in Single Shot mode. In addition, T13 can be started by events generated by the T12 Block, which set the run bit T13R. Please see the next sections for details on these modes. Software can clear timer T13 by writing 1 to the write-only bit T13RES. This operation only sets the timer contents to 0000H. No further actions will take place, for example, the timer run bit is not cleared. User's Manual CAPCOM6_X, V2.0 18-33 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Single-Shot Mode The run bit T13R is also influenced by hardware in Single-Shot mode. This mode is enabled through bit T13SSC. When this bit is set, the timer will stop when the current timer period is finished (see Figure 18-25). This is when the timer is cleared to 0000H after having reached the period value. fT13 Compare-Match T13 Count Period Value Compare Value Zero CC63ST T13SSC MCT05529 Figure 18-25 Single-Shot Operation of Timer T13 User's Manual CAPCOM6_X, V2.0 18-34 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Synchronization of T13 to T12 Timer T13 can be synchronized to a T12 event. Bitfields T13TEC and T13TED select the event which is used to start Timer T13. The selected event sets bit T13R via HW, and T13 starts counting. Combined with the Single-Shot mode, this feature can be used to generate a programmable delay after a T12 event. Figure 18-26 shows an example for the synchronization of T13 to a T12 event. Here, the selected event is a compare-match (compare value = 2) while counting up. The clocks of T12 and T13 can be different (other prescaler factor); the figure shows an example in which T13 is clocked with half the frequency of T12. fT12 Compare-Match T12 Count Period Value Compare Value Zero T13R T13 Count fT13 MCT05530 Figure 18-26 Synchronization of T13 to T12 Bitfield T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to the combinations shown in Table 18-6. Bitfield T13TED additionally specifies for which count direction of T12 the selected trigger event should be regarded (see Table 18-7). User's Manual CAPCOM6_X, V2.0 18-35 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Table 18-6 T13TEC 000B 001B 010B 011B 100B 101B 110B 111B Table 18-7 T13TED 00B 01B 10B 11B T12 Trigger Event Selection Selected Event None. T12 Compare Event on Channel 0. T12 Compare Event on Channel 1. T12 Compare Event on Channel 2. T12 Compare Event on any Channel (0, 1, 2). T12 Period-Match. T12 Zero-Match while counting up. Any Hall State Change. T12 Trigger Event Additional Specifier Selected Event Specifier Reserved, no action. Selected event is active while T12 is counting up. Selected event is active while T12 is counting down. Selected event is active independently of the count direction of T12. User's Manual CAPCOM6_X, V2.0 18-36 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.2.2 T13 Compare Modes Associated with Timer T13 is one compare channel, which can perform compare operations with regard to the contents of the T13 counter. Figure 18-27 gives an overview on the T13 channel in Compare Mode. The channel is connected to the T13 counter register via an Equal-to comparator, which generates a match signal when the contents of the counter matches the contents of the compare register. The channel consists of the comparator and a double register structure - the actual compare register, CC63R, feeding the comparator, and an associated shadow register, CC63SR, which is preloaded by software and transferred into the compare register when signal T13 shadow transfer, T13_ST, gets active. Providing a shadow register for the compare value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters. See also Section 18.8, which provides an overview on this functionality. fT13 Counter Register T13 Comp. =? Compare Match CM_63 Compare Register CC63R T13_ST Compare Shadow Register CC63SR MCA05531 Figure 18-27 T13 Channel Comparator Associated with the channel is a State Bit, CC63ST, which holds the status of the compare operation. This bit is set and reset according to certain conditions, which are explained in more detail in the following sections. Figure 18-28 gives an overview on the logic for the State Bit. User's Manual CAPCOM6_X, V2.0 18-37 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) T13R CM_63 T13_ZM T13_SSEP Set/Reset Control Logic State Bit CC63ST CC63ST CC63ST MCC63S/R MCB05532 Figure 18-28 T13 State Bit Block Diagram The inputs to the set/reset logic for the CC6xST bits are the timer run bit (T13R), the timer zero-match signal (T13_ZM), the end-of-single-shot mode signal (T13_SSEP), and the actual individual compare-match signal CM_63. In addition, the state bit can be set or reset by software via the set and reset bits, MCC63S and MCC63R. A modification of the State Bit CC63ST by hardware is only possible while Timer T13 is running (T13R = 1). If this is the case, the following rules apply for setting and resetting the State Bit in Compare Mode: State Bit CC63ST is set to 1 * * * with the next T13 clock (fT13) after a compare-match (T13 is always counting up) (i.e., when the counter is incremented above the compare value); with the next T13 clock (fT13) after a zero-match AND a parallel compare-match. with the next T13 clock (fT13) after a zero-match AND NO parallel compare-match. fT13 Compare-Match T13 Count Compare-Match Period Value Compare Value Zero CC63ST MCT05533 State Bit CC63ST is reset to 0 Figure 18-29 T13 Compare Operation Note: The waveforms in Figure 18-29 correspond to the T12-waveforms in Figure 18-11. User's Manual CAPCOM6_X, V2.0 18-38 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) T13 Compare Mode Output Path Figure 18-30 gives an overview on the signal path from the channel State Bit to its output pin in its simplest form. As illustrated, a user has a variety of controls to determine the desired output signal switching behavior in relation to the current state of the State Bit, CC63ST. Please refer to Section 18.7 for detailed information on the output modulation control. State Selection T13IM CC63ST State Bit CC63ST CC63ST CC63_O Output Modulation Level Select ECT13O PSL63 To Output Pin COUT63 COUT63_O COUT63PS MCA05534 Figure 18-30 CC63 Output Path The output line COUT63_O can generate a T13 PWM at the output pin COUT63. The signal CC63_O can be used to modulate the T12-related output signals with a T13 PWM. In order to decouple COUT63 from the internal modulation, the compare state leading to an active signal can be selected independently by bits T13IM and COUT63PS. User's Manual CAPCOM6_X, V2.0 18-39 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) T13 Compare Mode Registers Register CC63R is the actual compare registers for T13. The value stored in CC63R is compared to the count value of T13. Register CC63R can only be read by SW, the modification of the value is done by a shadow register transfer from the corresponding shadow register CC63SR. This register can be read and written by SW. CCU6_CC63R Channel 3 Compare Register 15 14 13 12 11 10 XSFR (E8B4H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC63V rh Field CC63V Bits [15:0] Type rh Description Channel 3 Compare Value Bitfield CC6xV contains the value that is compared to the T13 count value CCU6_CC63SR Channel 3 Comp. Shadow Reg. XSFR (E8B6H/--) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC63S rwh Field CC63S Bits [15:0] Type rwh Description Shadow Register for Channel 3 Compare Value The contents of CC63S are transferred to bitfield CC63V in register CC63R during a shadow transfer User's Manual CAPCOM6_X, V2.0 18-40 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.3 Timer Block Control Most features of timers T12 and T13 are controlled via the timer control registers TCTR0, TCTR2, and TCTR4. Register TCTR0 controls the basic functionality of both timers, T12 and T13. CCU6_TCTR0 Timer Control Register 0 15 14 13 12 11 10 XSFR (E8ACH/--) 9 T13CLK rw 8 7 6 5 4 Reset Value: 0000H 3 2 1 T12CLK rw 0 STE T13 T13R 13 PRE rh rh rw CTM CDIR rw rh STE T12 T12R 12 PRE rh rh rw Field STE131) Bits 13 Type rh Description Timer T13 Shadow Transfer Enable 0 The shadow register transfer is not requested 1 The shadow register transfer is requested Timer T13 Run Bit T13R starts and stops timer T13. It is set/reset by SW via bits T13RR or T13RS or it is reset by HW according to the function defined by bitfield T13SSC. 0 Timer T13 is stopped 1 Timer T13 is running Timer T13 Prescaler Enable Bit Enables the additional 1/256-prescaler of T13 0 The additional prescaler is disabled 1 The additional prescaler is enabled Timer T13 Input Clock Select Selects the input clock for Timer T13 which is derived from the CAPCOM6 input clock according to the equation: fT13 = fCC6/2 T13R2) 12 rh T13PRE 11 rw T13CLK [10:8] rw CTM 7 rw CDIR 6 rh User's Manual CAPCOM6_X, V2.0 18-41 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Field STE12 1) Bits 5 Type rh Description Timer T12 Shadow Transfer Enable 0 The shadow register transfer is not requested 1 The shadow register transfer is requested Timer T12 Run Bit T12R starts and stops Timer T12. It is set/reset by SW via bits T12RR or T12RS, or it is reset by HW according to the function defined by bitfield T12SSC. 0 Timer T12 is stopped 1 Timer T12 is running Timer T12 Prescaler Enable Bit Enables the additional 1/256-prescaler of T12 0 The additional prescaler is disabled 1 The additional prescaler is enabled Timer T12 Input Clock Select Selects the input clock for Timer T12 which is derived from the CAPCOM6 input clock according to the equation: fT12 = fCC6/2 T12R2) 4 rh T12PRE 3 rw T12CLK [2:0] rw 1) Bit STE12/STE13 is cleared when the shadow transfer takes place. 2) A concurrent set/reset action on T13R/T12R (from TxSSC, TxRR or TxRS) will have no effect. Bit T13R/T12R will remain unchanged. Note: A write action to the bitfields T12CLK/T13CLK or T12PRE/T13PRE is only taken into account while timer T12/T13 is not running (T12/T13R = 0). User's Manual CAPCOM6_X, V2.0 18-42 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register TCTR2 controls the single-shot and the synchronization functionality of both timers T12 and T13. CCU6_TCTR2 Timer Control Register 2 15 14 13 12 11 10 - XSFR (E8AEH/--) 9 8 7 6 T13 TED rw 5 4 Reset Value: 0000H 3 T13 TEC rw 2 1 0 T13 T12 SSC SSC rw rw Field T13TED Bits [6:5] Type rw Description Trigger Event Direction Control Bitfield T13TED additionally specifies for which count direction of T12 the selected trigger event should be regarded (see Table 18-7). Trigger Event Selection Bitfield T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to Table 18-6. Timer T13/T12 Single Shot Control This bit enables the Single-Shot Mode of T13/T12 0 Single-Shot Mode is disabled 1 Single-Shot Mode is enabled T13TEC [4:2] rw T13SSC T12SSC 1 0 rw Register TCTR4 provides software-control (independent set and clear conditions) for the run bits T12R and T13R. Furthermore, the timers can be reset (while running) and bits STE12 and STE13 can be controlled by software. Reading these bits always returns 0s. User's Manual CAPCOM6_X, V2.0 18-43 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) CCU6_TCTR4 Timer Control Register 4 15 14 13 12 11 10 XSFR (E8A6H/--) 9 8 7 6 5 4 - Reset Value: 0000H 3 2 1 0 T13 T13 STD STR w w T13 T13 T13 T12 T12 RES RS RR STD STR w w w w w DT T12 T12 T12 RES RES RS RR w w w w Field T13STD T12STD Bits 15 7 Type w Description Timer T13/T12 Shadow Transfer Disable 0 No action 1 STE13/STE12 is cleared without triggering the shadow transfer Timer T13/T12 Shadow Transfer Request 0 No action 1 STE13/STE12 is set, requesting the shadow transfer Timer T13/T12 Reset 0 No effect on T13/T12 1 The T13/T12 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T13RES/T12RES has no impact on bit T13R/T12R. Timer T13/T12 Run Bit Set Control1) Software can set bit T13R/T12R (start timer T13/T12) by writing to bit T13RS/T12RS. 0 T13R/T12R is not set 1 T13R/T12R is set, T13/T12 starts counting Timer T13/T12 Run Bit Reset Control1) Software can clear bit T13R/T12R (stop timer T13/T12) by writing to bit T13RR/T12RR. 0 T13R/T12R is not cleared 1 T13R/T12R is cleared, T13/T12 stops counting Dead-Time Counter Reset 0 No effect on the Dead-Time counters 1 All three Dead-Time counters are cleared and stopped T13STR T12STR 14 6 w T13RES T12RES 10 2 w T13RS T12RS 9 1 w T13RR T12RR 8 0 w DTRES 3 w 1) Setting the respective set- and reset-control bits together will not influence the associated timer. User's Manual CAPCOM6_X, V2.0 18-44 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) The channel state register CMPSTAT contains status bits displaying the current capture or compare state and control bits defining the active/passive state of a compare channel. CCU6_CMPSTAT Compare State Register 15 14 13 12 11 10 XSFR (E8A8H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 C C C C T13 CC CC CC OUT OUT OUT OUT IM 62PS 61PS 60PS 63PS 62PS 61PS 60PS rwh rwh rwh rwh rwh rwh rwh rwh CC CC CC CC CC CC CC POS POS POS 63ST 62ST 61ST 60ST 2 1 0 rh rh rh rh rh rh rh Field T13IM Bits 15 Type rwh Description T13 Inverted Modulation Control Bit T13IM inverts signal CC63_O for the modulation of the CC6x and COUT6x (x = 0, 1, 2) signals 0 CC63_O is not inverted 1 CC63_O is inverted for further modulation Passive State Select for Compare Output Bit COUT6xPS/CC6xPS selects the state of the compare channel, considered as the passive state. During the passive state, the passive level (defined in register PSLR) is driven by the output pin. 0 The compare output drives passive level while CC6xST is 0 1 The compare output drives passive level while CC6xST is 1 Note: In capture mode, these bits are not used. T13/T12 Compare State Bit Bits CC6xST monitor the state of the capture/ compare channels. Compare mode: 0 The timer count is less than the compare value 1 The timer count is greater than the comp. value Capture mode (channels 0 ... 2 only): 0 The selected edge has not yet been detected 1 The selected edge has been detected Sampled Hall Pattern Bits COUT63PS1) COUT62PS CC62PS COUT61PS CC61PS COUT60PS CC60PS 14 13 12 11 10 9 8 rwh CC63ST2) CC62ST CC61ST CC60ST 6 2 1 0 rh CCPOSx 5, 4, 3 rh 1) These bits have shadow bits and are updated in parallel to the capture/compare registers of T12 or T13, respectively. A read action targets the actually used values, whereas a write action targets the shadow bits. 2) These bits are set and reset according to the T12, T13 switching rules. User's Manual CAPCOM6_X, V2.0 18-45 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) The Compare Status Modification Register CMPMODIF provides software-control (independent set and clear conditions) for the channel state bits CC6xST. This feature enables the user to individually change the status of the output lines by software, for example when the corresponding compare timer is stopped. CCU6_CMPMODIF Comp. State Modification Reg. XSFR (E8AAH/--) 15 14 MCC 63R w 13 12 11 10 9 8 7 6 MCC 63S w 5 4 - Reset Value: 0000H 3 2 1 0 MCC MCC MCC 62R 61R 60R w w w MCC MCC MCC 62S 61S 60S w w w Field MCC63R MCC62R MCC61R MCC60R MCC63S MCC62S MCC61S MCC60S Bits 14 10 9 8 6 2 1 0 Type w Description Capture/Compare Channel x Status Reset Bit 0 No action 1 Bit CC6xST is cleared1) Capture/Compare Channel x Status Set Bit 0 No action 1 Bit CC6xST is set1) w 1) Setting the respective set- and reset-control bits together will toggle the associated status bit. User's Manual CAPCOM6_X, V2.0 18-46 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.4 Multi-Channel Mode The Multi-Channel mode offers the possibility to modulate all six T12-related output signals with one instruction. The bits in bitfield MCMOUT.MCMP are used to specify the outputs which may become active. If Multi-Channel mode is enabled (bit MODCTR.MCMEN = 1), only those outputs may become active, which have a 1 at the corresponding bit position in bitfield MCMP. This bitfield has its own shadow bitfield, MCMPS, which can be written by software. The transfer of the new value in MCMPS to the bitfield MCMP can be triggered by, and synchronized to, T12 or T13 events. This structure permits the software to write the new value, which is then taken into account by the hardware at a well-defined moment and synchronized to a PWM signal. This avoids unintended pulses due to unsynchronized modulation sources (T12, T13, software). SWSYN SW Update, STRMCM T12_ZM T13_ZM 0 Corr. Hall Evt. CM_CHE T13_PM T12_OM CM_61_UP T12_PM MUX Shadow Register MCMOUTS.MCMPS Shadow Transfer MCM_ST Switching Synchronization Register MCMOUTS.MCMP State Bit Outputs SWSEL Modulation Control Output Pins CC6x/COUT6x MCB05535 Figure 18-31 Multi-Channel Mode Block Diagram Figure 18-31 shows the modulation selection for the Multi-Channel mode. The event that triggers the update of bitfield MCMP is chosen by SWSEL. In order to synchronize the update of MCMP to a PWM generated by T12 or T13, bitfield SWSYN allows the selection of the synchronization event, which leads to the transfer from MCMPS to MCMP. Due to this structure, an update takes place with a new PWM period. A reminder flag, bit R, is set when the selected switching event occurs, and is reset when the transfer takes place. This flag can be monitored by software to check for the status of this logic. User's Manual CAPCOM6_X, V2.0 18-47 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) If it is explicitly desired, the update takes place immediately with the occurrence of the selected event when the direct synchronization mode is selected. The update can also be requested by software by writing to bitfield MCMPS with the shadow transfer request bit STRMCM set. By using the direct mode and bit STRMCM, the update takes place completely under software control. The event selection and synchronization options are summarized in Table 18-8 and Table 18-9. Table 18-8 SWSEL 000B 001B 010B 011B 100B 101B 11xB Multi-Channel Mode Trigger Event Selection Selected Event (see register CCU6_MCMCTR)1) None Correct Hall Event (CM_CHE) at pins CCPOS6x T13 Period-Match (T13_PM) T12 One-Match while counting down (T12_OM) T12 Compare Event of Channel 1 while counting up (CM_61_UP; see Section 18.5 and Figure 18-34). Phase delay function. T12 Period-Match while counting up (T12_PM) Reserved, no action 1) Software control is always possible. Table 18-9 SWSYN 00B 01B 10B 11B Multi-Channel Mode Trigger Event Synchronization Synchronization Event (see register CCU6_MCMCTR) Direct Mode: the trigger event directly causes the shadow transfer T13 Zero-Match T12 Zero-Match while counting up Reserved, no action User's Manual CAPCOM6_X, V2.0 18-48 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register MODCTR contains control bits enabling the modulation of the corresponding output signal by PWM patterns generated by timers T12 and T13. Furthermore, the Multi-Channel mode can be enabled as additional modulation source for the output signals. CCU6_MODCTR Modulation Control Register 15 ECT 13O rw 14 13 12 11 10 XSFR (E8C0H/--) 9 8 7 MCM EN rw 6 5 4 Reset Value: 0000H 3 2 1 0 T13MODEN rw T12MODEN rw Field ECT13O Bits 15 Type rw Description Enable Compare Timer T13 Output 0 Signal COUT63 is forced to 0 1 Signal COUT63 can switch as programmed T13/T12 Modulation Enable These bits enable the modulation of the corresponding compare channel(s) by a PWM pattern generated by timer T13 or T12. 0 No modulation by T13/T12 1 Corresponding output is modulated by a T13/T12 PWM pattern T13MODEN[5:0] and T12MODEN[5:0] correspond (left to right) to: COUT62, CC62, COUT61, CC61, COUT60, CC60. Multi-Channel Mode Enable Enables the modulation of the output signals by a multi-channel pattern according to bitfield MCMOUT 0 The modulation is disabled 1 The modulation is enabled T13MODEN T12MODEN [13:8] [5:0] rw MCMEN 7 rw Note: Registers MCMOUT, MCMOUTS, and MCMCTR are also related to MultiChannel Mode operation. User's Manual CAPCOM6_X, V2.0 18-49 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.5 Hall Sensor Mode For Brushless DC-Motors, usually the Multi-Channel Mode is used, as the modulation patterns need to be output to properly control the motor. These patterns need to be output in relation to the angular position of the motor. For this, usually Hall sensors or Back-EMF sensing are used to determine the angular rotor position. The CAPCOM6 provides three inputs, CC6POS0 ... CC6POS2, which can be used as inputs for the Hall sensors or the Back-EMF detection signals. There is a strong correlation between the motor position and the output modulation pattern. When a certain position of the motor has been reached, indicated by the sampled Hall sensor inputs (the Hall pattern), the next, pre-determined Modulation pattern has to be output. Because of different machine types, the modulation pattern for driving the motor can vary. Therefore, it is wishful to have a wide flexibility in defining the correlation between the Hall pattern and the corresponding Modulation pattern. The CAPCOM6 offers this by having a register which contains the actual current Hall pattern (CURH), the next expected Hall pattern (EXPH) and the corresponding output pattern (MCMP). A new Modulation pattern is output when the sampled Hall inputs match the expected ones (EXPH). To detect the next rotation phase (segment for block commutation), the CAPCOM6 monitors the Hall inputs for changes. When the next expected Hall pattern is detected, the next corresponding Modulation pattern is output. To provide for noise immunity (to a certain extend), the CAPCOM6 offers the possibility to introduce a sampling delay for the Hall inputs. In addition, it compares the sampled Hall signals to the current Hall pattern (CURH) to provide for some tolerance in case of short spikes. For the Hall and Modulation patterns, a double-register structure is implemented. While register MCMOUT holds the actually used values, its shadow register MCMOUTS can be loaded by software from a pre-defined table, holding the appropriate Hall and Modulation patterns for the given motor control. A transfer from the shadow register into register MCMOUT can take place when a correct Hall pattern change is detected, that is, when the sampled Hall pattern matches the expected one. Software can then load the next values into register MCMOUTS. It is also possible by software to force a transfer from MCMOUTS into MCMOUT. User's Manual CAPCOM6_X, V2.0 18-50 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.5.1 Hall Pattern Compare Logic Figure 18-32 gives an overview on the double-register structure and the pattern compare logic. Software writes the next modulation pattern (MCMPS) and the corresponding current (CURHS) and expected (EXPHS) Hall patterns into the shadow register MCMOUTS. Register MCMOUT holds the actually used values. The modulation pattern MCMP is provided to the Output Modulation Control block. The current (CURH) and expected (EXPH) Hall patterns are compared to the sampled Hall sensor inputs (pins CC6POSx) by comparators. Sampling of the inputs and the evaluation of the comparator outputs is controlled by signal HCRDY (Hall Compare Ready), which is detailed in the next section. SW Write CURHS SW Write EXPHS SW Write MCMPS Register MCMOUTS Shadow Transfer MCM_ST CURH EXPH MCMP Register MCMOUT Shadow Transfer CM_CHE CC6POS0..2 Sample To Output Modulation Comp. =? Comp. =? Comb. Logic HCRDY Wrong Hall Event CM_WHE MCA05536 Correct Hall Event CM_CHE HCRDY Figure 18-32 Hall Pattern Compare Logic When the sampled Hall pattern matches the expected one (EXPH), signal CM_CHE (Correct Hall Event) is generated. When the sampled Hall pattern matches the current one (CURH), no signal is generated, as this is a normal case after a spike on the input line. If the sampled pattern matches neither EXPH nor CURH, signal CM_WHE is generated, which indicates a wrong Hall event. At every correct Hall event (CM_CHE), the next Hall patterns are transferred from the shadow register MCMOUTS into MCMOUT, and a new Hall pattern with its corresponding output pattern can be loaded (from a predefined table) by software into MCMOUTS. For the Modulation patterns, signal MCM_ST is used to trigger the transfer. This signal can be generated through signal CM_CHE (see Figure 18-31). Loading this User's Manual CAPCOM6_X, V2.0 18-51 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) shadow register can also be done by a write action on MCMOUTS with bit STRHP = 1. In case of a phase delay (generated by T12 channel 1), a new pattern is applied when the Multi-Channel mode shadow transfer MCM_ST (indicated by bit STR) occurs. 18.5.2 Sampling of the Hall Pattern The Hall sensor inputs (CC6POSx) are monitored with the module clock (fCC6) via an edge detection block. When a level change is detected on any one of the three inputs, a signal is generated. In order to suppress spikes on the Hall inputs due to high di/dt in rugged inverter environment, a hardware noise filter can be used. This noise filtering is performed using the Dead-Time Counter DTC0. For this function, the mode control bitfields MSELx for the T12 Channels must all be programmed to `1000'. The output signal of the edge detection block is used to trigger DTC0. It is reloaded, starts counting, and thus generates a delay. An output signal, DTC0_O, is generated when the counter reaches the value one. This signal is used as the input sampling and compare evaluation signal HCRDY (see Figure 18-32). This feature provides a noise filter by delay. Most disturbances, such as switching spikes and signal bouncing, can be eliminated this way. When an input signal change was detected, the inputs are sampled a certain time later, determined by the reload value of DTC0. They are then compared to the current and expected Hall patterns. If the sampled pattern matches the current pattern (CURH), the detected input signal change was due to a noise spike (which is not visible anymore), and no further action will be triggered. If the sampled pattern matches the expected one (EXPH), the signal change was a correct Hall event, and signal CM_CHE is generated to trigger further actions. However, when the sampled pattern matches none of CURH and EXPH, the detected input change lead to a wrong Hall pattern. Signal CM_WHE is generated to indicate this fault and to allow further appropriate actions. Figure 18-33 illustrates the noise filter logic. CCPOS60..62 Hall Compare Logic Edge Detect Dead-Time DTC0_O Gen. Block DTC0 HCRDY MCB05537 Figure 18-33 Hall Trigger Logic Block Diagram User's Manual CAPCOM6_X, V2.0 18-52 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.5.3 Brushless DC-Motor Control with Timer T12 Block The CAPCOM6 provides a mode for the Timer T12 Block especially targeted for convenient control of Brushless DC-Motors. This mode is selected by setting all MSELx bitfields of the three T12 Channels to 1000B. In this mode, illustrated in Figure 18-34, channel 0 is placed in capture mode, while channels 1 and 2 are in compare mode. fT12 Counter Register T12 Reset CM_CHE CM_61 CM_CHE Comp. =? Comp. =? CM_62 Capture Register CC60R Compare Register CC61R Compare Register CC62R CM_CHE Compare Shadow Register CC61SR Compare Shadow Register CC62SR MCA05538 Figure 18-34 T12 Block in Hall Sensor Mode The signal to transfer the new compare values from the shadow registers (CC6xSR) into the actual compare registers (CC6xR) is now taken from the Correct Hall Event Compare, CM_CHE. In addition, this signal triggers a capture of the current T12 contents into register CC60R, and then forces a reset of T12 to 0000H. The same signal is also used to perform the shadow transfer of the new T12 period value. Note: In this mode, the shadow transfer signal T12_ST is not generated. Shadow bits, such as the PSLy bits, will not be transferred to their main registers. To program the main registers, SW needs to write to these registers while Timer T12 is stopped. In this case, a SW write actualizes both registers. User's Manual CAPCOM6_X, V2.0 18-53 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Hall Event captures and resets T12 CC62 Comp. T12 Count CC61 Comp. 0000H CC6POS0 CC6POS1 CC6POS2 CURH EXPH MCMP CC6x COUT6x 1 0 1 = 101 = 001 1 0 0 = 001 = 011 1 1 0 = 011 = 010 0 1 0 CC62 Compare for Time-Out CC61 Compare for Phase Delay 0 1 1 = 110 = 100 0 0 1 = 100 = ??? = 010 = 110 MCT05539 Figure 18-35 Brushless DC-Motor Control Example (all MSEL6x = 1000B) After the detection of a valid expected Hall pattern, the T12 count value is captured into channel 0 (representing the actual motor speed), and T12 is reset. When the timer reaches the compare value in channel 1, the next multi-channel state is switched by triggering the shadow transfer of bitfield MCMP (if enabled in bitfield SWEN). This trigger event can be combined with several conditions which are necessary to implement a noise filtering (correct Hall event) and to synchronize the next multi-channel state to the modulation sources (avoiding spikes on the output lines). This compare function of channel 1 can be used as a phase delay from the position sensor input signals to the switching of the output signals, which is necessary if a sensorless back-EMF technique is used instead of Hall sensors. The compare value in channel 2 can be used as a timeout trigger (interrupt), indicating that the motor's actual speed is far below the desired destination value, which can be caused by an abnormal load change. In this mode, the modulation of the outputs by T12 needs to be disabled (T12MODENx = 0). User's Manual CAPCOM6_X, V2.0 18-54 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) The capturing of the timer value in register CC60R, the shadow transfer from registers CC61SR to CC61R, from CC62SR to CC62R, and for the T12 period value, is done together with the reset event for T12. 18.5.4 Hall Mode Flags Depending on the Hall pattern compare operation, a number of flags are set in order to indicate the status of the module and to trigger further actions and interrupt requests. Flag CHE (Correct Hall Event) in register IS is set via signal CM_CHE when the sampled Hall pattern matches the expected one (EXPH). This flag can also be set by SW via setting bit SCHE in register ISS. If enabled through bit ENCHE (in register IEN), the set signal for CHE can also generate an interrupt request to the CPU. To clear flag CHE, SW needs to write a 1 to bit RCHE in register ISR. Flag WHE indicates a Wrong Hall Event. Its handling for flag setting and resetting as well as interrupt request generation is the same as described above for flag CHE. The implementation of flag STR is done in the same way as for CHE and WHE. This flag is set by HW via the shadow transfer signal MCM_ST (see also Figure 18-31). User's Manual CAPCOM6_X, V2.0 18-55 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Set SCHE CM_CHE _ >1 CHE Reset RCHE & ENCHE Interrupt Req. Set SWHE CM_WHE _ >1 WHE Reset RWHE & ENWHE SIDLE Interrupt Req. & ENIDLE _ >1 Set Reset RIDLE IDLE Clear MCMP Set SSTR MCM_ST _ >1 STR Reset RSTR & ENSTR Interrupt Req. MCA05540 Figure 18-36 Hall Mode Flag Logic Please note that for flags CHE, WHE, and STR, the interrupt request generation is triggered by the set signal for the flag. That means, a request can be generated even if the flag is already set. There is no need to reset the flag in order to enable further interrupt requests. The implementation for the IDLE flag is different. It is set by HW through signal CM_WHE if enabled by bit ENIDLE. Software can also set the flag via bit SIDLE. As long as bit IDLE is set, the modulation pattern field MCMP is cleared to force the outputs to the passive state. Flag IDLE must be reset by software through bit RIDLE in order to return to normal operation. To fully restart from IDLE mode, the transfer requests for the bitfields in register MCMOUTS to register MCMOUT have to be initiated by software via bits STRMCM and STRHP in register MCMOUTS. In this way, the release from IDLE mode is under software control, but can be performed synchronously to the PWM signal. User's Manual CAPCOM6_X, V2.0 18-56 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Hall Mode Registers Register MCMOUTS contains the shadow bitfields for the modulation and Hall patterns as well as control bits for a software-initiated shadow transfer. The contents of bitfields MCMPS, EXPHS, and CURHS are transferred into the corresponding fields of register MCMOUT when the associated shadow transfer signals are activated. CCU6_MCMOUTS Multi-Ch. Mode Outp. Shad. R. 15 STR HP w 14 13 12 CURHS rw 11 10 XSFR (E8CAH/--) 9 8 7 STR MCM w 6 5 4 Reset Value: 0000H 3 2 1 0 EXPHS rw MCMPS rw Field STRHP Bits 15 Type w Description Shadow Transfer Request for the Hall Patterns Setting this bit during a write action leads to an immediate update of bitfields CURH and EXPH by the value written to CURHS and EXPHS. This functionality permits an update triggered by SW. When read, this bit always delivers 0. 0 CURH and EXPH are updated according to the defined HW action. The write access to CURHS and EXPH does not modify bitfields CURH and EXPH. 1 CURH and EXPH are updated by the value written to bitfields CURHS and EXPHS. Current Hall Pattern Shadow Field CURHS is the shadow field for bitfield CURH. The bitfield is transferred to CURH when a correct Hall event is detected. Expected Hall Pattern Shadow Field EXPHS is the shadow field for bitfield EXPH. The bitfield is transferred to EXPH when a correct Hall event is detected. CURHS [11:13] rw EXPHS [10:8] rw User's Manual CAPCOM6_X, V2.0 18-57 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Field STRMCM Bits 7 Type w Description Shadow Transfer Request for MCMPS Setting this bit during a write action leads to an immediate update of bitfield MCMP by the value written to MCMPS. This functionality permits an update triggered by SW. When read, this bit always delivers 0. 0 MCMP is updated according to the defined HW action. The write access to MCMPS does not modify MCMP. 1 MCMP is updated by the value written to MCMPS. Multi-Channel PWM Pattern Shadow Field MCMPS is the shadow field for bitfield MCMP. The Multi-Channel shadow transfer is triggered according to the transfer conditions defined by register MCMCTR. MCMPS [5:0] rw Register MCMOUT holds the Modulation and Hall patterns that are currently used. CCU6_MCMOUT Multi-Ch. Mode Output Reg. 15 14 13 12 CURH rh 11 10 XSFR (E8CCH/--) 9 EXPH rh 8 7 6 R rh 5 4 Reset Value: 0000H 3 2 1 0 MCMP rh Field CURH1) Bits Type Description Current Hall Pattern CURH is written by a shadow transfer from bitfield CURHS. Bitfield CURH is compared to the sampled Hall pattern after every detected edge at the Hall sensor inputs CC6POSx. If the pattern match, the detected edge has been an invalid transition (e.g. due to a spike), and no further action is performed. If the sampled pattern do not either match CURH or EXPH, a Wrong Hall Event signal is set, which can trigger further actions. [13:11] rh User's Manual CAPCOM6_X, V2.0 18-58 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Field EXPH 1) Bits [10:8] Type rh Description Expected Hall Pattern EXPH is written by a shadow transfer from bitfield EXPHS. Bitfield EXPH is compared to the sampled Hall pattern after every detected edge at the Hall sensor inputs CC6POSx. If the pattern match, a Correct Hall Event signal is generated, which triggers further actions. Reminder Flag Indicates that the shadow transfer from bitfield MCMPS to MCMP has been requested by the selected trigger source. This bit is cleared while MCMEN = 0 and when the shadow transfer takes place. 0 No shadow transfer is requested 1 A shadow transfer from MCMPS to MCMP has been requested but not yet executed Multi-Channel Modulation Pattern MCMP contains the output modulation pattern for the Multi-Channel mode, which can set the corresponding output to the passive state. It is written by a shadow transfer from bitfield MCMPS. 0 The output is set to the passive state. 1 The output can deliver the PWM generated by T12 or T13 (according to register MODCTR). MCMP[5:0] corresponds to (left to right): COUT62, CC62, COUT61, CC61, COUT60, CC60. R 6 rh MCMP2) [5:0] rh 1) The bits in the bitfields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx (x = 0, 1, 2) in the order (EXPH.2, EXPH.1, EXPH.0), (CURH.2, CURH.1, CURH.0), (CCPOS2, CCPOS.1, CCPOS0). 2) While bit IS.IDLE = 1, bitfield MCMP is cleared. User's Manual CAPCOM6_X, V2.0 18-59 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register MCMCTR contains control bits for the Multi-Channel mode, controlling the output modulation pattern. CCU6_MCMCTR Multi-Ch. Mode Control Reg. 15 14 13 12 11 10 - XSFR (E8CEH/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 SWSEL rw 0 SWSYN rw Field SWSYN Bits [5:4] Type rw Description Switching Synchronization SWSYN triggers the shadow transfer from MCMPS to MCMP, if it has been requested before (flag R set) by an event selected by SWSEL. This permits the synchronization of the outputs to the source which is used for modulation (T12 or T13). See Table 18-9. Switching Selection SWSEL selects the trigger source (next multichannel event) for the shadow transfer from MCMPS to MCMP. The transfer takes place synchronously with the selected event. See Table 18-8. SWSEL [2:0] rw Note: The generation of the shadow transfer request by HW is only enabled if bit MCMEN = 1. User's Manual CAPCOM6_X, V2.0 18-60 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.6 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input pin CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g. to perform an emergency stop). The Trap Flag TRPF monitors the trap input and initiates the entry into the Trap State. It can also be set by SW. The Trap State Bit TRPS determines the effect on the outputs and controls the exit of the Trap State. When a trap condition is detected, both, the Trap Flag TRPF and the Trap State Bit TRPS, are set to 1. The Trap State is entered immediately. The output of the Trap State Bit TRPS leads to the Output Modulation Block and can there deactivate the outputs (set them to the passive state). Individual enable control bits for each of the six T12-related outputs and the T13-related output facilitate a flexible adaptation to the application needs (see Section 18.7). There are a number of different ways to exit the Trap State. This offers SW the option to select the operation which is best for the given application. Exiting the Trap State can be done either immediately when the trap condition is removed, or under software control, or synchronously to the PWM generated by either Timer T12 or Timer T13. Figure 18-37 gives an overview on the trap function. Both, the Trap Flag TRPF and the Trap State Bit TRPS, located in register IS, are set to 1 when input CTRAP is activated. The Trap Flag TRPF can also be set by SW via bit STRPF. In turn, the Trap State Bit TRPS will also be set through its Set/Reset Control block. As long as pin CTRAP = 0, TRPF and TRPS remain set and can not be cleared (assuming TRPPEN = 1). STRPF RTRPF Reg. IS Set CTRAP Set/Reset Control TRPPEN TRPM2 Reg. IS Set T12_ZM T13_ZM Set/Reset Control Reset Trap State TRPS To Output Modulation Reset Trap Flag TRPF TRPM1 TRPM0 MCB05541 Figure 18-37 Trap Logic Block Diagram User's Manual CAPCOM6_X, V2.0 18-61 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) The reset of TRPF is controlled by the mode control bit TRPM2 (located in the Trap Control Register TRPCTR). When TRPM2 = 0, TRPF is automatically cleared by HW when CTRAP returns to the inactive level (CTRAP = 1). When TRPM2 = 1, TRPF must be reset by SW after CTRAP has become inactive. The reset of TRPS is controlled by the mode control bits TRPM1 and TRPM0 (located in the Trap Control Register TRPCTR). A reset of TRPS terminates the Trap State and returns to normal operation. There are three options selected by TRPM1 and TRPM0. One is that the Trap State is left immediately when the Trap Flag TRPF is cleared, without any synchronization to timers T12 or T13. The other two options facilitate the synchronization of the termination of the Trap State to the count periods of either Timer T12 or Timer T13. Figure 18-38 gives an overview on the associated operation. T12 Count T13 Count TRPF TRPS TRPS TRPS CTRAP active Sync. to T12 Sync. to T13 No sync. MCT05542 Figure 18-38 Trap State Synchronization (with TRM2 = 0) User's Manual CAPCOM6_X, V2.0 18-62 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Trap Handling Registers Register TRPCTR controls the trap functionality. It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition. CCU6_TRPCTR Trap Control Register 15 14 13 12 11 10 XSFR (E8C2H/--) 9 8 7 6 5 4 - Reset Value: 0000H 3 2 1 0 TRP TRP EN PEN 13 rw rw TRPEN rw TRP TRP TRP M2 M1 M0 rw rw rw Field TRPPEN Bits 15 Type rw Description Trap Pin Enable Control 0 The trap input pin CTRAP is disabled. Software can generate a trap by setting bit TRPF. 1 The trap input pin CTRAP is enabled. A trap can be generated by SW by setting bit TRPF or by CTRAP = 0. Trap Enable Control for T13 Output Enables the trap functionality for the T13 output signal CC63. 0 The trap functionality is disabled. The output state is independent from bit TRPS. 1 The trap functionality is enabled. The output is set to the passive state while TRPS = 1. Trap Enable Control for T12 Outputs Enables the trap functionality for the individual output signals CC6x and COUT6x. 0 The trap functionality is disabled. The output state is independent from bit TRPS. 1 The trap functionality is enabled. The output is set to the passive state while TRPS = 1. TRPEN[5:0] corresponds to (left to right): COUT62, CC62, COUT61, CC61, COUT60, CC60. TRPEN13 14 rw TRPEN [13:8] rw User's Manual CAPCOM6_X, V2.0 18-63 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Field TRPM2 Bits 2 Type rw Description Trap Mode Control Bit 2 This bit controls whether the Trap State Exit is initiated by hardware or by software. 0 Trap State Exit initiated by HW. Bit TRPF is automatically cleared by HW if the input pin CTRAP becomes inactive (CTRAP = 1). 1 Trap State Exit initiated by SW. Bit TRPF must be reset by SW after the input CTRAP becomes inactive (CTRAP = 1). Trap Mode Control Bits 1, 0 These two bits control the termination of the Trap State. When the Trap Flag TRPF is reset to 0, the Trap State Bit TRPS is reset and the Trap State is left according to the following options: 00 T12 Synchronization: Reset of TRPS and Trap State Exit on a T12 Zero-Match (T12_ZM). 01 T13 Synchronization: Reset of TRPS and Trap State Exit on a T13 Zero-Match (T13_ZM). 10 Reserved, no action. 11 No Synchronization: Reset of TRPS and Trap State Exit immediately after reset of the Trap Flag TRPF. TRPM1, TRPM0 [1:0] rw User's Manual CAPCOM6_X, V2.0 18-64 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.7 Output Modulation Control The last block of the data path is the Output Modulation Control Logic. Here, all the modulation sources are combined and control the actual level of the output pins. In the following, the six T12-related outputs (CC6x, COUT6x) are discussed separately from the T13-related output CC63. Figure 18-39 gives an overview on the six control blocks and control signals regarding the T12-related outputs. Four individual modulation signals and their associated enable controls lead to each one of the blocks. The modulation signals CC6x_O and COUT6x_O come from the State Selection logic (see Figure 18-15) at the outputs of the three State Bits CC6xST. Signals MCMPy are the six outputs of the Multi-Channel Mode register MCMOUT (see Figure 18-31). Signal CC63_O is the T13-generated signal from the State Selection logic at the output of the State Bit CC63_ST (see Figure 18-30), and leads in parallel to all 6 blocks. The trap signal TRPS also is connected to all six blocks, and is the output of the Trap State bit (see Figure 18-37). While signals CC6x_O/COUT6x_O, CC63_O, and TRPS have individual enable controls for each of the six blocks, there is only one general enable signal, MCMEN, for the MCMPy signals. The output of each of the modulation control blocks is connected to a level select block, which offers the option to determine the actual output level of a pin, depending on the state of the output line. Figure 18-40 provides a closer look at one of the modulation and level select blocks. The logic, which combines the various signals, is designed such that only signals which are enabled by their respective enable signal can influence the output line, MCL_OUT. If one of the modulation signals CC6x_O/COUT6x_O, CC63_O, or MCMPx is enabled and is at passive state, output MCL_OUT is also in passive state, regardless of the state of the other enabled signals. Only if all enabled signals are in active state output MCL_OUT shows an active state. If the Trap State is active (TRPS = 1), then all outputs for which the trap signal is enabled (TRPENy = 1) are set to the passive state. The output MCL_OUT of the modulation control block is then used to select the actual level of the output, specified through the Passive State Select bit PSLy. When MCL_OUT is in the passive state, the level specified directly by PSLy is output. When MCL_OUT is in the active state, the inverted level of PSLy is output. The PSLy bits have shadow registers to allow for updates without undesired pulses on the output lines. The bits are updated with the T12 shadow transfer signal (T12_ST). A read action returns the actually used values, whereas a write action targets the shadow bits. Providing a shadow register for the PSL value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters (see also Section 18.8). User's Manual CAPCOM6_X, V2.0 18-65 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) CC60_O MCMP.0 CC63_O TRPS Modulation Control CC60 T12MODEN.0 MCMEN T13MODEN.0 TRPEN.0 MCL_OUT0 PSL0 Level Select To Output Pins CC60 COUT60_O MCMP.1 Modulation Control COUT60 T12MODEN.1 T13MODEN.1 TRPEN.1 MCL_OUT1 PSL1 Level Select COUT60 CC61_O MCMP.2 Modulation Control CC61 T12MODEN.2 T13MODEN.2 TRPEN.2 MCL_OUT2 PSL2 Level Select CC61 COUT61_O MCMP.3 Modulation Control COUT61 T12MODEN.3 T13MODEN.3 TRPEN.3 MCL_OUT3 PSL3 Level Select COUT61 CC62_O MCMP.4 Modulation Control CC62 T12MODEN.4 T13MODEN.4 TRPEN.4 MCL_OUT4 PSL4 Level Select CC62 COUT62_O MCMP.5 Modulation Control COUT62 T12MODEN.5 T13MODEN.5 TRPEN.5 MCL_OUT5 PSL5 Level Select COUT62 MCA05543 Figure 18-39 Output Modulation Overview User's Manual CAPCOM6_X, V2.0 18-66 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) WriteOnly CC6x_O COUT6x_O T12MODENy MCMPy MCMEN CC63_O T13MODENy TRPS TRPENy PSLy Shadow T12_ST Modulation Control Logic CC6x/ COUT6x ReadOnly PSLy 1 0 MCL_OUTy MUX To Output Pins CC6x COUT6x 0: Passive State 1: Active State x = 0, 1, 2 y = 0..5 MCA05544 To Other Blocks Figure 18-40 Output Modulation, Timer T12 Block WriteOnly PSL63 Shadow T13_ST ReadOnly COUT63_O ECT13O TRPS TRPEN13 Modulation Control Logic COUT63 PSL63 1 0 MCL_OUT63 MUX To Output Pin COUT63 0: Passive State 1: Active State To Other Blocks MCA05545 Figure 18-41 Output Modulation, Timer T13 Block User's Manual CAPCOM6_X, V2.0 18-67 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register PSLR defines the passive state level driven by the output pins of the module. The passive state level is the value that is driven by the port pin during the passive state of the output. During the active state, the corresponding output pin drives the active state level, which is the inverted passive state level. The passive state level permits to adapt the driven output levels to the driver polarity (inverted, not inverted) of the connected power stage. CCU6_PSLR Passive State Level Register 15 14 13 12 11 10 - XSFR (E8C4H/--) 9 8 7 PSL 63 rwh 6 5 4 Reset Value: 0000H 3 PSL rwh 2 1 0 Field PSL63 Bits 7 Type rwh Description T13 Output COUT63 Passive State Level Control This bitfield defines the passive level of the output pin COUT63. 0 The passive level is 0 1 The passive level is 1 T12 Outputs Passive State Level Control Defines the passive level driven by the module outputs during the passive state. 0 The passive level is 0 1 The passive level is 1 PSL[5:0] corresponds to (left to right): COUT62, CC62, COUT61, CC61, COUT60, CC60. PSL [5:0] rwh User's Manual CAPCOM6_X, V2.0 18-68 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.8 Shadow Register Transfer Control Figure 18-42 and Figure 18-43 give an overview on the shadow register structure and the shadow transfer signals, as well as on the read/write accessibility of the various registers. Providing a shadow register for values describing one PWM period facilitates a concurrent update by software for all relevant parameters. The next PWM period can run with a new set of parameters. Read (T12) PSLy T12_ST CC6xPS Read Write (T12) PSLy Shadow CC6xPS Shadow Write Read Period Register T12PR COUT6xPS Read Write Period Shadow Register T12PR COUT6xPS Shadow Write Read Compare Register CC6xR _ >1 Read Write Compare Shadow Register CC6xSR Other Modes (Hall, Capture, etc.) MCA05546 Figure 18-42 T12 Shadow Register and Transfer Signal Overview User's Manual CAPCOM6_X, V2.0 18-69 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Read PSL63 T13_ST T13IM Read Write PSL63 Shadow T13IM Shadow Write Read Period Register T13PR Write Period Shadow Register T13PR Read Compare Register CC63R Read Write Compare Shadow Register CC63SR MCA05547 Figure 18-43 T13 Shadow Register and Transfer Signal Overview User's Manual CAPCOM6_X, V2.0 18-70 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.9 Interrupt Generation The interrupt structure is shown in Figure 18-44. The HW interrupt event or the SW setting of the corresponding interrupt set bit (in register ISS) can trigger the interrupt generation. The interrupt pulse is generated independently from the interrupt flag in register IS. The interrupt flag can be reset by SW by writing to the corresponding bit in register ISR. If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can be generated on one of the four interrupt output lines, I0 ... I3, of the module. If more than one interrupt source is connected to the same interrupt node pointer (in register INP), the requests are combined to one common line. Interrupt Enable Register IEN 16 CC60 Cap./Com. Rising CC60 Cap./Com. Falling CC61 Cap./Com. Rising CC61 Cap./Com. Falling CC62 Cap./Com. Rising CC62 Cap./Com. Falling T12 One-Match T12 Period-Match T13 Compare-Match T13 Period-Match Correct Hall Event MCM Shadow Transfer Trap Condition Wrong Hall Event 16 Interrupt Set Register ISS Interrupt Status Register IS 16 I0 I1 I2 I3 CC6_INT CC6_EINT CC6_T12INT CC6_T13INT Interrupt Control Logic 14 Node Pointer Register INP 16 Interrupt Reset Register ISR MCA05548 Figure 18-44 Interrupt Structure Overview User's Manual CAPCOM6_X, V2.0 18-71 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) SW Request Reset Int. Flag Set _ >1 INPx & SW Request Set HW Interrupt Event a 6 _ >1 I0 Interrupt Enable _ >1 _ >1 6 _ >1 I1 HW Interrupt Event b SW Request Set Interrupt Enable Set Int. Flag & 6 _ >1 I2 6 From Other Interrupt Sources _ >1 I3 SW Request Reset MCA05549 Figure 18-45 Interrupt Structure Detail Interrupt Registers Register IS contains the individual interrupt request and status bits. This register can only be read, write actions have no impact on the contents of this register. Software can set or reset the bits individually by writing to register ISS (to set the bits) or to register ISR (to reset the bits). CCU6_IS Interrupt Status Register 15 14 13 12 11 10 XSFR (E8D0H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 IDLE WHE CHE rh rh rh TRP TRP T13 T13 T12 T12 ICC ICC ICC ICC ICC ICC S F PM CM PM OM 62F 62R 61F 61R 60F 60R rh rh rh rh rh rh rh rh rh rh rh rh Field IDLE Bits 14 Type rh Description IDLE State Flag If enabled (ENIDLE = 1), this bit is set together with bit WHE (Wrong Hall Event). It has to be reset by SW. 0 No action 1 Bitfield MCMP is cleared, the selected outputs are set to passive state User's Manual CAPCOM6_X, V2.0 18-72 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Field WHE Bits 13 Type rh Description Wrong Hall Event Flag 0 No wrong hall pattern yet 1 A transition to a wrong hall pattern (not the expected one) has occurred Correct Hall Event Flag 0 No correct (= expected) hall pattern yet 1 A transition to an expected hall pattern has occurred Trap State Bit 0 The Trap State is not active 1 The Trap State is active. Bit TRPS is set while bit TRPF = 1. It is reset according to the mode selected in register TRPCTR. Trap Flag The trap flag TRPF is set either by HW, if TRPPEN = 1 and CTRAP = 0, or by SW. If TRPM2 = 0, bit TRPF is reset by HW if the input CTRAP becomes inactive (TRPPEN = 1). If TRPM2 = 1, bit TRPF has to be reset by SW in order to leave the trap state. 0 The trap condition has not occurred 1 The trap condition has occurred (CTRAP = 0 or by SW) Timer T13 Period-Match Flag 0 No T13 Period-Match yet 1 A T13 Period-Match has occurred Timer T13 Compare-Match Flag 0 No T13 Compare-Match yet 1 A T13 Compare-Match has occurred Timer T12 Period-Match Flag 0 No T12 Period-Match yet 1 A T12 Period-Match has occurred while counting up Timer T12 One-Match Flag 0 No T12 One-Match yet 1 A T12 One-Match has been detected while counting down CHE 12 rh TRPS1) 11 rh TRPF 10 rh T13PM 9 rh T13CM 8 rh T12PM 7 rh T12OM 6 rh User's Manual CAPCOM6_X, V2.0 18-73 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Field ICC62F ICC61F ICC60F Bits 5 3 1 Type rh Description Capture, Compare-Match Falling Edge Flag In compare mode, a Compare-Match has been detected while T12 was counting down. In capture mode, a falling edge has been detected at the input CC6x (x = 0, 1, 2). 0 The event has not yet occurred 1 The event described above has occurred Capture, Compare-Match Rising Edge Flag In compare mode, a compare-match has been detected while T12 was counting up. In capture mode, a rising edge has been detected at the input CC6x (x = 0, 1, 2). 0 The event has not yet occurred 1 The event described above has occurred ICC62R ICC61R ICC60R 4 2 0 rh 1) During the trap state, the selected outputs are set to the passive state. Note: Not all bits in register IS can generate an interrupt. Other status bits have been added, which have a similar structure for their set and reset actions. Note: In compare mode (and hall mode), the timer-related interrupts are only generated while the timer is running (TxR = 1). In capture mode, the capture interrupts are also generated while the Timer T12 is stopped. User's Manual CAPCOM6_X, V2.0 18-74 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Registers ISS and ISR contain write-only bits corresponding to the interrupt and status flags in register IS (except for bit 11). By writing 1s to these bits, software can set (ISS) or clear (ISR) the associated flag(s). Reading these bits always returns 0s. Setting a bit in register ISS will set the corresponding flag in register IS and may trigger an interrupt request (if enabled and if available for that function). Setting a bit in register ISR will clear the corresponding flag in register IS. CCU6_ISS Interrupt Status Set Register 15 14 13 12 11 10 XSFR (E8D2H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 S S S IDLE WHE CHE w w w S S S S S S S S S S S TRP T13 T13 T12 T12 CC CC CC CC CC CC F PM CM PM OM 62F 62R 61F 61R 60F 60R w w w w w w w w w w w Field SIDLE SWHE SCHE STRPF ST13PM ST13CM ST12PM ST12OM SCC62F SCC61F SCC60F SCC62R SCC61R SCC60R Bits 14 13 12 10 9 8 7 6 5 3 1 4 2 0 Type w w w w w w w w w Description1) Set IDLE Flag Set Wrong Hall Event Flag Set Correct Hall Event Flag Set Trap Flag Set Timer T13 Period-Match Flag Set Timer T13 Compare-Match Flag Set Timer T12 Period-Match Flag Set Timer T12 One-Match Flag Set Capture, Compare-Match Falling Edge Flag w Set Capture, Compare-Match Rising Edge Flag 1) Writing 1 to one of these bits will set the associated flag. Writing 0 has no effect. User's Manual CAPCOM6_X, V2.0 18-75 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) CCU6_ISR Interrupt Status Reset Reg. 15 14 13 12 11 10 XSFR (E8D4H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 R R R IDLE WHE CHE w w w R R R R R R R R R R R TRP T13 T13 T12 T12 CC CC CC CC CC CC F PM CM PM OM 62F 62R 61F 61R 60F 60R w w w w w w w w w w w Field RIDLE RWHE RCHE RTRPF RT13PM RT13CM RT12PM RT12OM RCC62F RCC61F RCC60F RCC62R RCC61R RCC60R Bits 14 13 12 10 9 8 7 6 5 3 1 4 2 0 Type w w w w w w w w w Description1) Reset IDLE Flag Reset Wrong Hall Event Flag Reset Correct Hall Event Flag Reset Trap Flag Reset Timer T13 Period-Match Flag Reset Timer T13 Compare-Match Flag Reset Timer T12 Period-Match Flag Reset Timer T12 One-Match Flag Reset Capture, Compare-Match Falling Edge Flag w Reset Capture, Compare-Match Rising Edge Flag 1) Writing 1 to one of these bits will clear the associated flag. Writing 0 has no effect. Note: The set/clear bits in registers ISS and ISR can be written (set) via bit-operations (e.g. BSET), logical operations (e.g. OR), or single MOV-operations (e.g. executed via PEC). User's Manual CAPCOM6_X, V2.0 18-76 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) Register IEN contains the interrupt enable bits and a control bit to enable the automatic idle function in the case of a wrong hall pattern. Setting a bit in this register will enable the interrupt request (or defined function for a bit). Clearing a bit disables the interrupt request (or defined other function). CCU6_IEN Interrupt Enable Register 15 14 13 12 11 10 XSFR (E8D8H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 EN EN EN IDLE WHE CHE rw rw rw EN EN EN EN EN EN EN EN EN EN EN TRP T13 T13 T12 T12 CC CC CC CC CC CC F PM CM PM OM 62F 62R 61F 61R 60F 60R rw rw rw rw rw rw rw rw rw rw rw Field ENIDLE ENWHE ENCHE ENTRPF ENT13PM ENT13CM ENT12PM ENT12OM ENCC62F ENCC61F ENCC60F ENCC62R ENCC61R ENCC60R Bits 14 13 12 10 9 8 7 6 5 3 1 4 2 0 Type rw rw rw rw rw rw rw rw rw Description Enable Idle Flag Set Function Enable Wrong Hall Event Interrupt Enable Correct Hall Event Interrupt Enable Trap Flag Interrupt Enable T13 Period-Match Interrupt Enable T13 Compare-Match Interrupt Enable T12 Period-Match Interrupt Enable T12 One-Match Interrupt Enable Capture, Compare-Match Interrupt upon Falling Edge Enable Capture, Compare-Match Interrupt upon Rising Edge rw User's Manual CAPCOM6_X, V2.0 18-77 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) The interrupt sources of the CAPCOM6 module can be mapped to four interrupt nodes by programming the interrupt node pointer register CC6_INP. The encoding valid for all bitfields is shown in Table 18-10. CCU6_INP Interrupt Node Pointer Reg. 15 14 13 12 11 10 XSFR (E8D6H/--) 9 INP ERR rw 8 7 INP CHE rw 6 5 4 Reset Value: 3940H 3 2 1 0 INP T13 rw INP T12 rw INP CC62 rw INP CC61 rw INP CC60 rw Field INPT13 Bits Type Description Interrupt Node Pointer for Timer13 Interrupt This bitfield selects the interrupt request line for source T13CM and/or source T13PM. Interrupt Node Pointer for Timer12 Interrupts This bitfield selects the interrupt request line for source T12OM and/or source T12PM. Interrupt Node Pointer for Error Interrupts This bitfield selects the interrupt request line for source TRPF and/or source WHE. Interrupt Node Pointer for the CHE Interrupt This bitfield selects the interrupt request line for source CHE and/or source STR. Interrupt Node Pointer for Channel x Interrupts This bitfield selects the interrupt request line for source CC6xR and/or source CC6xF. [13:12] rw INPT12 [11:10] rw INPERR [9:8] rw INPCHE [7:6] rw INPCC62 INPCC61 INPCC60 [5:4] [3:2] [1:0] rw Table 18-10 Encoding of Interrupt Node Pointer Bitfields Bitfield INPxx 00B 01B 10B 11B Interrupt Output Line to be Activated I0 I1 I2 I3 The default assignment of the interrupt sources to the nodes and their corresponding control registers are listed in Table 18-11. User's Manual CAPCOM6_X, V2.0 18-78 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) All interrupt control registers have the same structure. The basic register layout is shown below, Table 18-11 lists the associated addresses. CCU6_xIC CAPCOM6 Intr. Ctrl. Reg. 15 14 13 12 11 10 ESFR (Table 18-11) 9 8 GPX rw 7 6 5 4 Reset Value: - - 00H 3 2 1 0 CCy CCy IR IE rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Table 18-11 CAPCOM6 Default Interrupt Node Register Assignment Source of Interrupt Channel 0 Interrupts Channel 1 Interrupts Channel 2 Interrupts Correct Hall Pattern Interrupt Emergency Interrupts Timer T12 Interrupts Timer T13 Interrupts Interrupt Request Nr. I0 I0 I0 I1 I1 I2 I3 CCU6_T12IC CCU6_T13IC F190H F198H CCU6_EIC F188H Interrupt Control Register CCU6_IC Register Address F140H User's Manual CAPCOM6_X, V2.0 18-79 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.10 Suspend Mode In suspend mode, the functional clock fCC6 of the module kernel is stopped. The registers can still be accessed by the CPU (read only). This mode is useful for debugging purposes, e.g. where the current device status should be `frozen' in order to get a snapshot of the internal values. In suspend mode, the timers T12 and T13 are not running. The suspend mode is non-intrusive concerning the register bits. This means, register bits are not changed by hardware when entering or leaving the suspend mode. Software actions are also not required. In suspend mode, all registers can be accessed by read instructions for debugging purposes. The suspend mode can be entered when the suspend mode is requested, the suspend mode is enabled and the module has reached a safe, deterministic state (like the timer stop conditions in single shot mode). This behavior avoids critical situations if a power inverter is connected to the module's outputs. The suspend state has no direct influence on the output signals. User's Manual CAPCOM6_X, V2.0 18-80 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Unit 6 (CAPCOM6) 18.11 Interfaces of the CAPCOM6 Unit The CAPCOM6 units is connected to its environment in different ways. Internal Connections The 4 interrupt request lines of the CAPCOM6 unit are connected to the interrupt control block. The period match signal of timer T13 (T13_PM) is connected to the ADC, as a possible trigger source for injected conversions. External Connections The signals of the CAPCOM6 unit are connected with input/output ports of the XC167. These ports may provide capture trigger signals from the external system, issue compare output signals to external circuitry, or accept control input signals. System Control Unit (SCU) fCC6 CC6DIS CAPCOM6 Module CC60 COUT60 CC61 CCOUT61 CC62 I0 I1 I2 I3 CCOUT62 CCOUT63 CTRAP CC6POS0 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 P1H.0 P1H.1 P1H.2 MCA05550 CCU6IRQ Interrupt Control CCU6EIRQ CCU6T12IRQ CCU6T13IRQ ADC CCU6T13PM CC6POS1 CC6POS2 Figure 18-46 CAPCOM6 Unit Interfaces User's Manual CAPCOM6_X, V2.0 18-81 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19 Asynchronous/Synchronous Serial Interface (ASC) The XC167 contains two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. The following sections present the general features and operations of such an ASC module. The final section describes the actual implementation of the two ASC modules including their interconnections with other on-chip modules. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. The ASC provides the following features and functions. Features and Functions * Full-duplex asynchronous operating modes - 8- or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baudrate from 2.5 Mbit/s to 50 bit/s (@ 40 MHz module clock fASC) Multiprocessor Mode for automatic address/data byte detection Loopback capability Support for IrDA data transmission up to 115.2 kbit/s maximum Half-duplex 8-bit synchronous operating mode - Baudrate from 5 Mbit/s to 202 bit/s (@ 40 MHz module clock fASC) Double buffered transmitter/receiver Interrupt generation - On a transmitter buffer empty condition - On a transmit last bit of a frame condition - On a receiver buffer full condition - On an error condition (frame, parity, overrun error) Autobaud detection unit for asynchronous operating modes - Detection of standard baudrates 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, and 230400 bit/s - Detection of non-standard baudrates - Detection of Asynchronous Modes - 7 bit, even parity; 7 bit, odd parity; 8 bit, even parity; 8 bit, odd parity; 8 bit, no parity - Automatic initialization of control bits and baudrate generator after detection - Detection of a serial two-byte ASCII character frame FIFO - 8-stage receive FIFO (RXFIFO), 8-stage transmit FIFO (TXFIFO) - Independent control of RXFIFO and TXFIFO - 9-bit FIFO data width - Programmable Receive/Transmit Interrupt Trigger Level - Receive and transmit FIFO filling level indication - Overrun and Underflow error generation * * * * * * * * Figure 19-1 shows all functional relevant interfaces associated with the ASC Kernel. User's Manual ASC_X8, V2.1 19-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Bus Interface fASC Clock Control ASCxDIS Module Product Interface Address Decoder TIR TBIR Interrupt Control RIR EIR ABSTIR ABDETIR ASC Module (Kernel) TxD Port Control RxD MCA05432 Figure 19-1 ASC Interface Diagram User's Manual ASC_X8, V2.1 19-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.1 Operational Overview Figure 19-2 shows a block diagram of the ASC with its operating modes (Asynchronous and Synchronous Mode). Asynchronous Mode fASC Prescaler / Fractional Divider Autobaud Detection fDIV Baudrate Timer Serial Port Control RxD MUX IrDA Decoding Receive / Transmit Buffers and Shift Registers MUX IrDA Decoding TxD Synchronous Mode fASC 2 or 3 Baudrate Timer Serial Port Control TxD Shift Clock Receive / Transmit Buffers and Shift Registers RxD RxD MCB05433 Figure 19-2 Block Diagram of the ASC The ASC supports full-duplex asynchronous communication with up to 2.5 Mbit/s and half-duplex synchronous communication with up to 5 Mbit/s (@ 40 MHz module clock). In Synchronous Mode, data are transmitted or received synchronous to a shift clock that is generated by the microcontroller. In Asynchronous Mode, either 8- or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is provided to distinguish address bytes from data bytes. User's Manual ASC_X8, V2.1 19-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Testing is supported by a loop-back option. A 13-bit baudrate timer with a versatile input clock divider circuitry provides the serial clock signal. In a Special Asynchronous Mode, the ASC supports IrDA data transmission up to 115.2 kbit/s with fixed or programmable IrDA pulse width. Autobaud Detection allows to detect asynchronous data frames with its baudrate and mode with automatic initialization of the baudrate generator and the mode control bits. A transmission is started by writing to the transmit buffer register TBUF. The selected operating mode determines the number of data bits that will actually be transmitted, so that, bits written to positions 9 through 15 of register TBUF are always insignificant. Data transmission is double-buffered, so a new character may be written to the transmit buffer register before the transmission of the previous character is complete. This allows the transmission of characters back-to-back without gaps. Data reception is enabled by the Receiver Enable Bit REN. After reception of a character has been completed, the received data can be read from the (read-only) receive buffer register RBUF; the received parity bit can also be read if provided by the selected operating mode. Bits in the upper half of RBUF that are not valid in the selected operating mode will be read as zeros. Data reception is double-buffered, so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register. In all modes, receive overrun error detection can be selected through bit OEN. When enabled, the overrun error status flag OE and the error interrupt request line EIR will be activated when the receive buffer register has not been read by the time reception of a ninth character is complete. The previously received character in the receive buffer is overwritten. The Loopback Mode (selected by bit LB) allows the data currently being transmitted to be received simultaneously in the receive buffer. This may be used to test serial communication routines at an early stage without having to provide an external network. Note: In Loopback Mode, the alternate input/output functions of the associated port pins are not necessary. Note: Serial data transmission or reception is only possible when the Baudrate Generator Run bit R is set. Otherwise, the serial interface is idle. Note: Do not program the Mode Control bitfield M to one of the reserved combinations to avoid unpredictable behavior of the serial interface. The operating mode of the serial channel ASC is controlled by its control register ASCx_CON. This register contains control bits for mode and error check selection, and status flags for error identification. User's Manual ASC_X8, V2.1 19-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.2 Asynchronous Operation Asynchronous Mode supports full-duplex communication in which both transmitter and receiver use the same data frame format and the same baudrate. Data is transmitted on line TxD and received on line RxD. IrDA data transmission/reception is supported up to 115.2 kbit/s. Figure 19-3 shows the block diagram of the ASC when operating in Asynchronous Mode. CON.FDE CON.BRS 13-bit Reload Register Fractional Divider MUX fASC 2 3 fDIV 13-bit Baudrate Timer 16 fBR fBRT ABSTIR Autobaud Start Int. Autobaud Detect Int. CON.R Autobaud Detection ABDETIR CON.ODD CON.STP CON.M CON.FE CON.PE CON.OE RIR TIR Receive Int. Request Transmit Int. Request Transmit Buffer Int. Request Error Int. Request CON.REN CON.FEN CON.PEN CON.OEN CON.LB Shift Clock Serial Port Control FIFO Shift Clock Control TBIR EIR MUX Sampling Receive Shift Register Receive Buffer Reg. RBUF Transmit Shift Register Transmit Buffer Reg. TBUF IrDA Coding MUX IrDA Decoding MUX Internal Bus MUX RxD 1 1 TxD MCA05434 Figure 19-3 User's Manual ASC_X8, V2.1 Asynchronous Mode of Serial Channel ASC 19-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.2.1 Asynchronous Data Frames 8-Bit Data Frames 8-bit data frames consist of either eight data bits D7 ... D0 (M = 001B), or seven data bits D6 ... D0 plus an automatically generated parity bit (M = 011B). Parity may be odd or even, depending on bit ODD. An even parity bit will be set if the modulo-2-sum of the 7 data bits is 1. An odd parity bit will be cleared in this case. Parity checking is enabled via bit PEN (always OFF in 8-bit data mode). The parity error flag PE will be set, along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit RBUF.7. 10-/11-bit UART Frame 8 Data Bits 1 M = 001B Start D0 Bit LSB 0 D1 D2 D3 D4 D5 D6 1 (1st) (2nd) D7 Stop Stop MSB Bit Bit 10-/11-bit UART Frame 7 Data Bits 1 M = 011B Start D0 Bit LSB 0 D1 D2 D3 D4 D5 1 (1st) (2nd) D6 Parity Stop Stop MSB Bit Bit Bit MCT05435 Figure 19-4 Asynchronous 8-Bit Frames User's Manual ASC_X8, V2.1 19-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 9-Bit Data Frames 9-bit data frames consist of either nine data bits D8 ... D0 (M = 100B), eight data bits D7 ... D0 plus an automatically generated parity bit (M = 111B), or eight data bits D7 ... D0 plus wake-up bit (M = 101B). Parity may be odd or even, depending on bit ODD. An even parity bit will be set if the modulo-2-sum of the 8 data bits is 1. An odd parity bit will be cleared in this case. Parity checking is enabled via bit PEN (always OFF in 9-bit data and wake-up mode). The parity error flag PE will be set, along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit RBUF.8. 11-/12-bit UART Frame 9 Data Bits 1 Start D0 Bit LSB 0 D1 D2 D3 D4 D5 D6 D7 1 (1st) (2nd) Bit 9 Stop Stop Bit Bit CON.M = 100B : Bit 9 = Data Bit D8 CON.M = 101B : Bit 9 = Wake-up Bit CON.M = 111B : Bit 9 = Parity Bit MCT05436 Figure 19-5 Asynchronous 9-Bit Frames In wake-up mode, received frames are transferred to the receive buffer register only if the 9th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will be transferred. This feature may be used to control communication in a multi-processor system: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte to identify the target slave. An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte, but is a 0 for a data byte; so, no slave will be interrupted by a data `byte'. An address `byte' will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the eight LSBs of the received character (the address). The addressed slave will switch to 9-bit data mode (such as by clearing bit M[0]), to enable it to also receive the data bytes that will be coming (having the wake-up bit cleared). The slaves not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes. User's Manual ASC_X8, V2.1 19-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) IrDA Frames The modulation schemes of IrDA are based on standard asynchronous data transmission frames. The asynchronous data format in IrDA Mode (M = 010B) is defined as follows: 1 start bit/8 data bits/1 stop bit The coding/decoding of/to the asynchronous data frames is shown in Figure 19-6. In general, during IrDA transmissions, UART frames are encoded into IR frames and vice versa. A low level on the IR frame indicates an "LED off" state. A high level on the IR frame indicates an "LED on" state. For a 0-bit in the UART frame, a high pulse is generated. For a 1-bit in the UART frame, no pulse is generated. The high pulse starts in the middle of a bit cell and has a fixed width of 3/16 of the bit time. The ASC also allows the length of the IrDA high pulse to be programmed. Further, the polarity of the received IrDA pulse can be inverted in IrDA Mode. Figure 19-6 shows the non-inverted IrDA pulse scheme. UART Frame 8 Data Bits Start Bit 0 1 0 1 0 0 1 1 0 Stop Bit 1 IR Frame 8 Data Bits Start Bit 0 1 0 1 0 0 1 1 0 Stop Bit 1 Bit Time 1/2-bit Time Pulse Width = 3/16-bit Time (or variable length) MCT05437 Figure 19-6 IrDA Frame Encoding/Decoding The ASC IrDA pulse mode/width register PMW contains the 8-bit IrDA pulse width value and the IrDA pulse width mode select bit. This register is required in the IrDA operating mode only. User's Manual ASC_X8, V2.1 19-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.2.2 Asynchronous Transmission Asynchronous transmission begins at the next overflow of the divide-by-16 baudrate timer (transition of the baudrate clock fBR), if bit R is set and data has been loaded into TBUF. The transmitted data frame consists of three basic elements: * * * Start bit Data field (eight or nine bits, LSB first, including a parity bit, if selected) Delimiter (one or two stop bits) Data transmission is double-buffered. When the transmitter is idle, the transmit data loaded in the transmit buffer register is immediately moved to the transmit shift register, thus freeing the transmit buffer for the next data to be sent. This is indicated by the transmit buffer interrupt request line TBIR being activated. TBUF may now be loaded with the next data, while transmission of the previous data continues. The transmit interrupt request line TIR will be activated before the last bit of a frame is transmitted, that is, before the first or the second stop bit is shifted out of the transmit shift register. Note: The transmitter output pin TxD must be configured for alternate data output. 19.2.3 * * * * * Transmit FIFO Operation The transmit FIFO (TXFIFO) provides the following functionality: Enable/disable control Programmable filling level for transmit interrupt generation Filling level indication FIFO clear (flush) operation FIFO overflow error generation The 8-stage transmit FIFO is controlled by the TXFCON control register. When bit TXFEN is set, the transmit FIFO is enabled. The interrupt trigger level defined by TXFITL defines the filling level of the TXFIFO at which a transmit buffer interrupt TBIR or a transmit interrupt TIR is generated. These interrupts are always generated when the filling level of the transmit FIFO is equal to or less than the value stored in TXFITL. Bitfield TXFFL in the FIFO status register ASCx_FSTAT indicates the number of entries that are actually written (valid) in the TXFIFO. Therefore, the software can verify, in the interrupt service routine, for instance, how many bytes can still be written into the transmit FIFO via register TBUF without getting an overrun error. The transmit FIFO cannot be accessed directly. All data write operations into the TXFIFO are executed by writing into the TBUF register. User's Manual ASC_X8, V2.1 19-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) TXFCON.TXFITL = 0011 B Byte 6 Byte 5 Byte 5 Byte 4 Byte 4 Byte 4 3 Byte Byte 3 Byte 3 2 Byte Byte 3 Byte 2 Byte 2 Byte 2 Byte 2 Byte 6 Byte 5 Byte 4 Byte 3 Byte 6 Byte 5 Byte 4 Byte 6 Byte 5 Byte 7 Byte 7 Byte 6 Byte 6 Byte 5 Byte 7 TXFIFO Empty FSTAT. 0000 TXFFL 0101 0100 0011 0010 0010 0001 0000 TxD TBIR Byte 1 Byte 2 TBIR Byte 3 TIR TBIR Byte 4 TIR TBIR Byte 5 TIR TBIR Byte 6 TIR TBIR Byte 7 TIR Writing Byte 1 Writing Byte 2 Writing Byte 3 Writing Byte 4 Writing Byte 5 Writing Byte 6 Writing Byte 7 MCT05438 Figure 19-7 Transmit FIFO Operation Example The example in Figure 19-7 shows a typical 8-stage transmit FIFO operation. In this example seven bytes are transmitted via the TxD output line. The transmit FIFO interrupt trigger level TXFITL is set to 0011B. The first byte written into the empty TXFIFO via TBUF is directly transferred into the transmit shift register and is not written into the FIFO. A transmit buffer interrupt will be generated in this case. After byte 1, bytes 2 to 6 are written into the transmit FIFO. After the transfer of byte 3 from the TXFIFO into the transmit shift register of the ASC, 3 bytes remain in the TXFIFO. Therefore, the value of TXFITL is reached and a transmit buffer interrupt will be generated at the beginning and a transmit interrupt at the end of the byte 3 serial transmission. During the serial transmission of byte 4, another byte (byte 7) is written into the TXFIFO (TBUF write operation). Finally, after the start of the serial transmission of byte 7, the TXFIFO is again empty. User's Manual ASC_X8, V2.1 19-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) If the TXFIFO is full and additional bytes are written into TBUF, the error interrupt will be generated with bit OE set. In this case, the data byte that was last written into the transmit FIFO is overwritten and the transmit FIFO filling level TXFFL is set to maximum. The TXFIFO can be flushed or cleared by setting bit TXFFLU in register ASCx_TXFCON. After this TXFIFO flush operation, the TXFIFO is empty and the transmit FIFO filling level TXFFL is set to 0000B. A running serial transmission is not aborted by a receive FIFO flush operation Note: The TXFIFO is flushed automatically with a reset operation of the ASC module and if the TXFIFO becomes disabled (resetting bit TXFEN) after it was previously enabled. User's Manual ASC_X8, V2.1 19-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.2.4 Asynchronous Reception Asynchronous reception is initiated by a falling edge (1-to-0 transition) on line RxD, provided that bits R and REN are set. The receive data input line RxD is sampled at 16 times the rate of the selected baudrate. A majority decision of the 7th, 8th, and 9th sample determines the effective bit value. This avoids erroneous results that may be caused by noise. If the detected value is not a 0 when the start bit is sampled, the receive circuit is reset and waits for the next 1-to-0 transition at line RxD. If the start bit proves valid, the receive circuit continues sampling and shifts the incoming data frame into the receive shift register. When the last stop bit has been received, the content of the receive shift register are transferred to the receive data buffer register RBUF. Simultaneously, the receive interrupt request line RIR is activated after the 9th sample in the last stop bit time slot (as programmed), regardless of whether valid stop bits have been received or not. The receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input line. Note: The receiver input pin RxD must be configured for input. Asynchronous reception is stopped by clearing bit REN. A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Start bits that follow this frame will not be recognized. Note: In wake-up mode, received frames are transferred to the receive buffer register only if the 9th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will be transferred. 19.2.5 * * * * * Receive FIFO Operation The receive FIFO (RXFIFO) provides the following functionality: Enable/disable control Programmable filling level for receive interrupt generation Filling level indication FIFO clear (flush) operation FIFO overflow error generation The 8-stage receive FIFO is controlled by the RXFCON control register. When bit RXFEN is set, the receive FIFO is enabled. The interrupt trigger level defined by RXFITL defines the filling level of RXFIFO at which a receive interrupt RIR is generated. RIR is always generated when the filling level of the receive FIFO is equal to or greater than the value stored in RXFITL. Bitfield RXFFL in the FIFO status register ASCx_FSTAT indicates the number of bytes that have been actually written into the FIFO and can be read out of the FIFO by a user program. User's Manual ASC_X8, V2.1 19-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) The receive FIFO cannot be accessed directly. All data read operations from the RXFIFO are executed by reading the RBUF register. RXFCON.RXFITL = 0011 B Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Content of FSTAT.RXFFL 0000 Byte 1 0001 Byte 1 0010 Byte 2 Byte 1 0011 Byte 3 Byte 2 Byte 1 0100 0001 0010 0100 0000 Byte 4 Byte 4 Byte 5 Byte 4 RXFIFO Empty RxD Byte 1 Byte 2 Byte 3 RIR Byte 4 RIR Byte 5 Byte 6 RIR Read RBUF (Byte 1) Read RBUF (Byte 2) Read RBUF (Byte 3) Read RBUF (Byte 4) Read RBUF (Byte 5) Read RBUF (Byte 6) MCT05439 Figure 19-8 Receive FIFO Operation Example The example in Figure 19-8 shows a typical 8-stage receive FIFO operation. In this example, six bytes are received via the RxD input line. The receive FIFO interrupt trigger level RXFITL is set to 0011B. Therefore, the first receive interrupt RIR is generated after the reception of byte 3 (RXFIFO is filled with three bytes). After the reception of byte 4, three bytes are read out of the receive FIFO. After this read operation, the RXFIFO still contains one byte. RIR becomes again active after two more bytes (byte 5 and 6) have been received (RXFIFO filled again with 3 bytes). Finally, the FIFO is cleared after three read operation. If the RXFIFO is full and additional bytes are received, the receive interrupt RIR and the error interrupt EIR will be generated with bit OE set. In this case, the data byte last written into the receive FIFO is overwritten. With the overrun condition, the receive FIFO filling level RXFFL is set to maximum. If a RBUF read operation is executed with the RXFIFO User's Manual ASC_X8, V2.1 19-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) enabled but empty, an error interrupt EIR will be generated as well with bit OE set. In this case, the receive FIFO filling level RXFFL is set to 0000B. If the RXFIFO is available but disabled (RXFEN = 0) and the receive operation is enabled (REN = 1), the asynchronous receive operation is functionally equivalent to the asynchronous receive operation of the ASC module. The RXFIFO can be flushed or cleared by setting bit RXFFLU in register RXFCON. After this RXFIFO flush operation, the RXFIFO is empty and the receive FIFO filling level RXFFL is set to 0000B. The RXFIFO is flushed automatically with a reset operation of the ASC module and if the RXFIFO becomes disabled (resetting bit RXFEN) after it was previously enabled. Resetting bit REN without resetting RXFEN does not affect (reset) the RXFIFO state. This means that the receive operation of the ASC is stopped, in this case, without changing the content of the RXFIFO. After setting REN again, the RXFIFO with its content is again available. Note: After a successful autobaud detection sequence (if implemented), the RXFIFO should be flushed before data is received. User's Manual ASC_X8, V2.1 19-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.2.6 FIFO Transparent Mode In Transparent Mode, a specific interrupt generation mechanism is used for receive and transmit buffer interrupts. In general, in Transparent Mode, receive interrupts are always generated if data bytes are available in the RXFIFO. Transmit buffer interrupts are always generated if the TXFIFO is not full. The relevant conditions for interrupt generation in Transparent Mode are: * * FIFO filling levels Read/write operations on the RBUF/TBUF data register Interrupt generation for the receive FIFO depends on the RXFIFO filling level and the execution of read operations of register RBUF (see Figure 19-9). Transparent Mode for the RXFIFO is enabled when bits RXTMEN and RXFEN in register ASCx_RXFCON are set. Content of RXFCON. RXFFL 0000 0001 0010 0011 0100 0011 0010 0001 0001 RxD Byte 1 RIR (1) Byte 2 Byte 3 Byte 4 RIR (2) RIR (3) RIR (4) Read RBUF Read Read Byte 1 Byte 2 Read Read Byte 3 Byte 4 MCT05440 Figure 19-9 Transparent Mode Receive FIFO Operation If the RXFIFO is empty, a receive interrupt RIR is always generated when the first byte is written into an empty RXFIFO (RXFFL changes from 0000B to 0001B). If the RXFIFO is filled with at least one byte, the occurrence of further receive interrupts depends on the read operations of register RBUF. The receive interrupt RIR will always be activated after a RBUF read operation if the RXFIFO still contains data (RXFFL is not equal to 0000B). If the RXFIFO is empty after a RBUF read operation, no further receive interrupt will be generated. If the RXFIFO is full (RXFFL = maximum) and additional bytes are received, an error interrupt EIR will be generated with bit OE set. In this case, the data byte last written into the receive FIFO is overwritten. If a RBUF read operation is executed with the RXFIFO enabled but empty (underflow condition), an error interrupt EIR will be generated as well, with bit OE set. If the RXFIFO is flushed in Transparent Mode, the software must take care that a previous pending receive interrupt is ignored. User's Manual ASC_X8, V2.1 19-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Note: The Receive FIFO Interrupt Trigger Level bitfield RXFITL is a don't care in Transparent Mode. Interrupt generation for the transmit FIFO depends on the TXFIFO filling level and the execution of write operations to the register TBUF. Transparent Mode for the TXFIFO is enabled when bits TXTMEN and TXFEN are set. A transmit buffer interrupt TBIR is always generated when the TXFIFO is not full (TXFFL not equal to maximum) after a byte has been written into register ASCx_TBUF. TBIR is also activated after a TXFIFO flush operation or when the TXFIFO becomes enabled (TXTMEN and TXFEN set) when it was previously disabled. In these cases, the TXFIFO is empty and ready to be filled with data. If the TXFIFO is full (TXFFL = maximum) and an additional byte is written into TBUF, no further transmit buffer interrupt will be generated after the TBUF write operation. In this case the data byte last written into the transmit FIFO is overwritten and an overrun error interrupt (EIR) will be generated with bit OE set. Note: The Transmit FIFO Interrupt Trigger Level bitfield TXFITL is a don't care in Transparent Mode. 19.2.7 IrDA Mode The duration of the IrDA pulse is normally 3/16 of a bit period. The IrDA standard also allows the pulse duration to be independent of the baudrate or bit period. In this case, the width of the transmitted pulse always corresponds to the 3/16 pulse width at 115.2 kbit/s, which is 1.627 s. Either fixed or bit-period-dependent IrDA pulse width generation can be selected. The IrDA pulse width mode is selected by bit IRPW. In case of fixed IrDA pulse width generation, the lower eight bits in register PMW are used to adapt the IrDA pulse width to a fixed value such as 1.627 s. The fixed IrDA pulse width is generated by a programmable timer as shown in Figure 19-10. PWM Start Timer tIPW fASC 8-bit Timer IrDA Pulse MCA05441 Figure 19-10 Fixed IrDA Pulse Generation The IrDA pulse width can be calculated according the formulas given in Table 19-1. Note: The name PMW in the formulas of Table 19-1 represents the contents of the pulse mode/width register PMW (PW_VALUE), taken as an unsigned 8-bit integer. User's Manual ASC_X8, V2.1 19-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 19-1 PMW 1 ... 255 Formulas for IrDA Pulse Width Calculation PMW_IPMW 0 Formulas 3 t IPW = --------------------------------------16 x Baudrate t IPW min = ( PMW >> 1 ) -------------------------------f ASC 1 t IPW = PMW -------------f ASC The contents of PW_VALUE further define the minimum IrDA pulse width (tIPW min) that is still recognized as a valid IrDA pulse during a receive operation. This function is independent of the selected IrDA pulse width mode (fixed or variable) which is defined by bit IRPW. The minimum IrDA pulse width is calculated by a shift right operation of PMW bit 7-0 by one bit divided by the module clock fASC. Note: If IRPW is cleared (fixed IrDA pulse width), PW_VALUE must be a value which assures that tIPW > tIPW min. Table 19-2 gives three examples for typical frequencies of fASC. Table 19-2 IrDA Pulse Width Adaption to 1.627 s PMW 33 65 fASC 20 MHz 40 MHz tIPW 1.650 s 1.625 s Error +1.4% -0.1% tIPW min 0.8 s 0.8 s 19.2.8 RxD/TxD Data Path Selection in Asynchronous Modes The data paths for the serial input and output data in Asynchronous Mode are affected by several control bits in the registers CON and ABCON as shown in Figure 19-11. The Synchronous Mode operation is not affected by these data path selection capabilities. The input signal from RxD passes an inverter which is controlled by bit RXINV. The output signal of this inverter is used for the Autobaud Detection and may bypass the logic in the Echo Mode (controlled by bit ABEM). Further, two multiplexers are in the RxD input signal path for providing the Loopback Mode capability (controlled by bit LB) and the IrDA receive pulse inversion capability (controlled by bit RxDI). Depending on the Asynchronous Mode (controlled by bitfield M), output signal or the RxD input signal in Echo Mode (controlled by bit ABEM) is switched to the TxD output via an inverter (controlled by bit TXINV). User's Manual ASC_X8, V2.1 19-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Autobaud Detection ABCON RXINV RxD MUX MUX MUX TXINV ABEM IrDA Coding IrDA Decode MUX MUX MUX ASC Asynch. Mode Logic CON LB RxDI TxD M MCA05442 Figure 19-11 RxD/TxD Data Path in Asynchronous Modes Note: In Echo Mode the transmit output signal is blocked by the Echo Mode output multiplexer. Figure 19-11 shows that it is not possible to use an IrDA coded receiver input signal for Autobaud Detection. User's Manual ASC_X8, V2.1 19-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.3 Synchronous Operation Synchronous Mode supports half-duplex communication, basically for simple I/O expansion via shift registers. Data is transmitted and received via line RxD while line TxD outputs the shift clock. Synchronous Mode is selected with bitfield M = 000B. Eight data bits are transmitted or received synchronous to a shift clock generated by the internal baudrate generator. The shift clock is active only as long as data bits are transmitted or received. 13-bit Reload Register fASC 2 3 MUX fDIV 13-bit Baudrate Timer fBRT 4 fBR R BRS M = 000B Shift Clock REN OEN LB TxD Serial Port Control FIFO Shift Clock Control 0 1 OE RIR TIR TBIR EIR Receive Int. Request Transmit Int. Request Transmit Buffer Int. Request Error Int. Request RxD MUX Receive Shift Register Transmit Shift Register Receive FIFO Reg. RBUF Transmit FIFO Reg. TBUF Internal Bus MCA05443 Figure 19-12 Synchronous Mode of Serial Channel ASC User's Manual ASC_X8, V2.1 19-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.3.1 Synchronous Transmission Synchronous transmission begins within four state times after data has been loaded into TBUF, provided that bit R is set and bit REN is cleared (half-duplex, no reception). Exception: in Loopback Mode (bit LB set), REN must be set for reception of the transmitted byte. Data transmission is double-buffered. When the transmitter is idle, the transmit data loaded into TBUF is immediately moved to the transmit shift register, thus freeing TBUF for more data. This is indicated by the transmit buffer interrupt request line TBIR being activated. TBUF may now be loaded with the next data, while transmission of the previous continuous. The data bits are transmitted synchronous with the shift clock. After the bit time for the eighth data bit, both the TxD and RxD lines will go high, the transmit interrupt request line TIR is activated, and serial data transmission stops. Note: Pin TxD must be configured for alternate data output in order to provide the shift clock. Pin RxD must also be configured for output during transmission. 19.3.2 Synchronous Reception Synchronous reception is initiated by setting bit REN. If bit R is set, the data applied at RxD is clocked into the receive shift register synchronous to the clock that is output at TxD. After the eighth bit has been shifted in, the contents of the receive shift register are transferred to the receive data buffer RBUF, the receive interrupt request line RIR is activated, the receiver enable bit REN is reset, and serial data reception stops. Note: Pin TxD must be configured for alternate data output in order to provide the shift clock. Pin RxD must be configured as alternate data input. Synchronous reception is stopped by clearing bit REN. A currently received byte is completed, including the generation of the receive interrupt request and an error interrupt request, if appropriate. Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission. If a previously received byte has not been read out of a full receive buffer at the time the reception of the next byte is complete, both the error interrupt request line EIR and the overrun error status flag OE will be activated/set, provided the overrun check has been enabled by bit OEN. 19.3.3 Synchronous Timing Figure 19-13 shows timing diagrams of the ASC Synchronous Mode data reception and data transmission. In idle state, the shift clock level is high. With the beginning of a synchronous transmission of a data byte, the data is shifted out at RxD with the falling edge of the shift clock. If a data byte is received through RxD, data is latched with the rising edge of the shift clock. Between two consecutive receive or transmit data bytes, one shift clock cycle (fBR) delay is inserted. User's Manual ASC_X8, V2.1 19-20 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Receive/Transmit Timing Shift Latch Shift Clock (TxD) Transmit Data (RxD) Receive Data (RxD) Continuous Transmit Timing Shift Clock (TxD) Transmit Data (RxD) D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 Data Bit n Data Bit n+1 Data Bit n+2 Shift Shift Valid Data n Valid Data n+1 Valid Data n+2 1. Byte Receive Data (RxD) D0 D1 D2 D3 D4 1. Byte D5 D6 D7 D0 D1 2. Byte D2 D3 2. Byte MCT05444 Figure 19-13 ASC Synchronous Mode Waveforms User's Manual ASC_X8, V2.1 19-21 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.4 Baudrate Generation The serial channel ASC has its own dedicated 13-bit baudrate generator with reload capability, allowing baudrate generation independent of other timers. The baudrate generator is clocked with a clock (fDIV) derived via a prescaler from the ASC input clock fASC. The baudrate timer counts downwards and can be started or stopped through the baudrate generator run bit R. Each underflow of the timer provides one clock pulse to the serial channel. The timer is reloaded with the value stored in its 13-bit reload register each time it underflow. The resulting clock fBRT is again divided by a factor for the baudrate clock (16 in Asynchronous Modes and 4 in Synchronous Mode). The prescaler is selected by the bits BRS and FDE. In addition to the two fixed dividers, a fractional divider prescaler unit is available in the Asynchronous Modes that allows selection of prescaler divider ratios of n/512 with n = 0 ... 511. Therefore, the baudrate of ASC is determined by the module clock, the content of FDV, the reload value of BG, and the operating mode (asynchronous or synchronous). Register ASCx_BG is the dual-function Baudrate Generator/Reload register. Reading ASCx_BG returns the contents of the timer BR_VALUE (bits 15 ... 13 return zero), while writing to BG always updates the reload register (bits 15 ... 13 are insignificant). An autoreload of the timer with the contents of the reload register is performed each time ASCx_BG is written to. However, if bit R is cleared at the time a write operation to ASCx_BG is performed, the timer will not be reloaded until the first instruction cycle after bit R was set. For a clean baudrate initialization, ASCx_BG should be written only if R = 0. If ASCx_BG is written while R = 1, unpredictable behavior of the ASC may occur during running transmit or receive operations. The ASC baudrate timer reload register ASCx_BG contains the 13-bit reload value for the baudrate timer in Asynchronous and Synchronous modes. 19.4.1 Baudrate in Asynchronous Mode For Asynchronous Mode, the baudrate generator provides a clock fBRT with sixteen times the rate of the established baudrate. Every received bit is sampled at the 7th, 8th, and 9th cycle of this clock. The clock divider circuitry, which generates the input clock for the 13-bit baudrate timer, is extended by a fractional divider circuitry that allows adjustment for more accurate baudrate and the extension of the baudrate range. The baudrate of the baudrate generator depends on the following bits and register values: * * * * Input clock fASC Selection of the baudrate timer input clock fDIV by bits FDE and BRS If bit FDE is set (fractional divider): value of register ASCx_FDV Value of the 13-bit reload register ASCx_BG User's Manual ASC_X8, V2.1 19-22 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) The output clock of the baudrate timer with the reload register is the sample clock in the Asynchronous Modes of the ASC. For baudrate calculations, this baudrate clock fBR is derived from the sample clock fDIV by a division by 16. The ASC fractional divider register ASCx_FDV contains the 9-bit divider value for the fractional divider (Asynchronous Mode only). It is also used for reference clock generation of the autobaud detection unit. FDE Fractional Divider MUX 13-bit Reload Register 16 fBR Baudrate Clock Sample Clock fASC 2 3 fDIV 13-bit Baudrate Timer fBRT R FDE BRS 0 0 1 BRS 0 1 X Selected Divider 2 3 Fractional Divider MCA05445 Figure 19-14 ASC Baudrate Generator Circuitry in Asynchronous Modes Using the Fixed Input Clock Divider The baudrate for asynchronous operation of serial channel ASC when using the fixed input clock divider ratios (FDE = 0) and the required reload value for a given baudrate can be determined by the following formulas: BG represents the contents of the reload bitfield BR_VALUE, taken as unsigned 13-bit integer. The maximum baudrate that can be achieved for the Asynchronous Modes when using the two fixed clock divider and a module clock of 40 MHz is 1.25 Mbit/s. Table 19-4 lists various commonly used baudrates together with the required reload values and the deviation errors compared to the intended baudrate. Note: FDE must be 0 to achieve the baudrates in Table 19-3. The deviation errors given in the table are rounded. Using a baudrate crystal will provide correct baudrates without deviation errors. User's Manual ASC_X8, V2.1 19-23 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 19-3 FDE 0 Asynchronous Baudrate Formulas Using the Fixed Input Clock Dividers BRS 0 BG 0 ... 8191 Formula ASC Baudrate = ----------------------------------32 x ( BG + 1 ) ASC BG = --------------------------------------- - 1 32 x Baudrate f f 1 ASC Baudrate = ----------------------------------48 x ( BG + 1 ) ASC BG = --------------------------------------- - 1 48 x Baudrate f f Table 19-4 Baudrate 1.25 Mbit/s 19.2 kbit/s 9600 bit/s 4800 bit/s 2400 bit/s 1200 bit/s Typical Asynchronous Baudrates Using the Fixed Input Clock Dividers BRS = 0, fASC = 40 MHz --+0.1% / -1.3% +0.1% / -0.6% +0.1% / -0.2% +0.1% / -0.0% +0.0% / -0.0% 0000H 0040H / 0041H 0081H / 0082H 0103H / 0104H 0207H / 0208H 0410H / 0411H NA +0.9% / -1.3% +0.9% / -0.2% +0.3% / -0.2% +0.0% / -0.2% +0.0% / -0.0% BRS = 1, fASC = 40 MHz NA 002AH / 002BH 0055H / 0056H 00ACH / 00ADH 015AH / 015BH 02B5H / 02B6H Deviation Error Reload Value Deviation Error Reload Value Using the Fractional Divider When the fractional divider is selected, the input clock fDIV for the baudrate timer is derived from the module clock fASC by a programmable divider. If bit FDE is set, the fractional divider is activated. It divides fASC by a fraction of n/512 for any value of n from 0 to 511. If n = 0, the divider ratio is 1, which means that fDIV = fASC. In general, the fractional divider allows the baudrate to be programmed with much more accuracy than with the two fixed prescaler divider stages. Note: BG represents the contents of the reload bitfield BR_VALUE, taken as an unsigned 13-bit integer. Note: FDV represents the contents of the fractional divider register FD_VALUE taken as an unsigned 9-bit integer. User's Manual ASC_X8, V2.1 19-24 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 19-5 FDE 1 BRS - Async. Baudrate Formulas Using the Fractional Input Clock Divider BG 1 ... 8191 FDV 1 ... 511 Formula f ASC FDV Baudrate = ----------- x ----------------------------------512 16 x ( BG + 1 ) ASC Baudrate = ----------------------------------16 x ( BG + 1 ) 0 f Table 19-6 Typical Asynchronous Baudrates Using the Fractional Input Clock Divider BG 04H 04H 0EH 0EH FDV 076H 03BH 076H 03BH Resulting Baudrate 115.234 kbit/s 57.617 kbit/s 38.411 kbit/s 19.206 kbit/s Deviation 0.02% 0.02% 0.02% 0.02% fASC 40 MHz Desired Baudrate 115.2 kbit/s 57.6 kbit/s 38.4 kbit/s 19.2 kbit/s User's Manual ASC_X8, V2.1 19-25 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.4.2 Baudrate in Synchronous Mode For synchronous operation, the baudrate generator provides a clock with four times the rate of the established baudrate (see Figure 19-15). 13-bit Reload Register 2 MUX fASC 3 R BRS fDIV 13-bit Baudrate Timer fBRT 4 Shift / Sample Clock BRS 0 1 Selected Divider 2 3 MCA05446 Figure 19-15 ASC Baudrate Generator Circuitry in Synchronous Mode The baudrate for synchronous operation of serial channel ASC can be determined by the formulas as shown in Table 19-7. Table 19-7 BRS 0 Synchronous Baudrate Formulas BG 0 ... 8191 Formula ASC Baudrate = -------------------------------8 x ( BG + 1 ) f ASC BG = ----------------------------------- - 1 8 x Baudrate f 1 ASC Baudrate = ----------------------------------12 x ( BG + 1 ) f ASC BG = --------------------------------------- - 1 12 x Baudrate f Note: BG represents the contents of the reload bitfield BR_VALUE, taken as an unsigned 13-bit integers. The maximum baudrate that can be achieved in Synchronous Mode when using a module clock of 40 MHz is 5 Mbit/s. User's Manual ASC_X8, V2.1 19-26 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.5 19.5.1 Autobaud Detection General Operation Autobaud Detection provides a capability to recognize the mode and the baudrate of an asynchronous input signal at RxD. Generally, the baudrates to be recognized must be known by the application. With this knowledge always a set of nine baudrates can be detected. The Autobaud Detection is not designed to calculate a baudrate of an unknown asynchronous frame. Figure 19-16 shows how the Autobaud Detection is integrated into its Asynchronous Mode configuration. The RxD data line is an input to the autobaud detection unit. The clock fDIV, generated by the fractional divider, is used by the autobaud detection unit as time base. After successful recognition of baudrate and Asynchronous Mode of the RxD data input signal, bits in register ASCx_CON and the value of register ASCx_BG in the baudrate timer are set to the appropriate values, and the ASC can start immediately with the reception of serial input data. Asynchronous Mode Prescaler / Fractional Divider Autobaud Detection fASC fDIV Baudrate Timer Serial Port Control RxD MUX IrDA Decoding Receive / Transmit Buffers and Shift Registers MUX IrDA Decoding TxD MCA05447 Figure 19-16 Asynchronous Mode Block Diagram Note: Autobaud detection is not available in Synchronous Mode. The following sequence must be executed to start the autobaud detection unit: * * * * * * Definition of the baudrates to be detected: standard or non-standard baudrates Programming of the prescaler/fractional divider to select a specific value of fDIV Starting the prescaler/fractional divider (setting bit R) Preparing the interrupt system Enabling the autobaud detection (setting bit EN and the interrupt enable bits in ABCON for interrupt generation, if required) Polling interrupt request flag or waiting for the autobaud detection interrupt 19-27 V2.0, 2004-04 User's Manual ASC_X8, V2.1 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.5.2 Serial Frames for Autobaud Detection The Autobaud Detection is based on the serial reception of a specific two-byte serial frame. This serial frame is build up by the two ASCII bytes "at" or "AT" ("aT" or "At" are not allowed). Both byte combinations can be detected in five types of asynchronous frames. Figure 19-17 and Figure 19-18 show the serial frames which are detected at least. Note: Some other two-byte combinations will be defined too. 7 Bit, Even Parity `a' = 61H 1 Start `t' = 74H 1 1 1 1 Start 0 0 0 0 0 0 1 0 1 1 1 0 1 Parity Stop Parity Stop 7 Bit, Odd Parity `a' = 61H 1 Start `t' = 74H 1 1 0 1 Start 0 0 0 0 0 0 1 0 1 1 1 1 1 Parity Stop Parity Stop 8 Bit, No Parity `a' = 61H 1 Start `t' = 74H 1 1 0 1 Stop Start 0 0 0 0 0 0 1 0 1 1 1 0 1 Stop 8 Bit, Even Parity `a' = 61H 1 Start `t' = 74H 1 1 0 1 1 Start 0 0 0 0 0 0 1 0 1 1 1 0 0 1 Parity Stop Parity Stop 8 Bit, Odd Parity `a' = 61H 1 Start `t' = 74H 1 1 0 0 1 Start 0 0 0 0 0 0 1 0 1 1 1 0 1 1 Parity Stop Parity Stop MCT05448 Figure 19-17 Two-Byte Serial Frames with ASCII `at' User's Manual ASC_X8, V2.1 19-28 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 7 Bit, Even Parity `A' = 41H 1 Start `T' = 54H 0 1 0 1 Start 0 0 0 0 0 0 1 0 1 0 1 1 1 Parity Stop Parity Stop 7 Bit, Odd Parity `A' = 41H 1 Start `T' = 54H 0 1 1 1 Start 0 0 0 0 0 0 1 0 1 0 1 0 1 Parity Stop Parity Stop 8 Bit, No Parity `A' = 41H 1 Start `T' = 54H 0 1 0 1 Stop Start 0 0 0 0 0 0 1 0 1 0 1 0 1 Stop 8 Bit, Even Parity `A' = 41H 1 Start `T' = 54H 0 1 0 0 1 Start 0 0 0 0 0 0 1 0 1 0 1 0 1 1 Parity Stop Parity Stop 8 Bit, Odd Parity `A' = 41H 1 Start `T' = 54H 0 1 0 1 1 Start 0 0 0 0 0 0 1 0 1 0 1 0 0 1 Parity Stop Parity Stop MCT05449 Figure 19-18 Two-Byte Serial Frames with ASCII `AT' 19.5.3 Baudrate Selection and Calculation Autobaud Detection requires some calculations concerning the programming of the baudrate generator and the baudrates to be detected. Two steps must be considered: * * Defining the baudrate(s) to be detected Programming of the baudrate timer prescaler - setup of the clock rate of fDIV User's Manual ASC_X8, V2.1 19-29 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) In general, the baudrate generator in Asynchronous Mode is build up by two parts (see also Figure 19-14): * * The clock prescaler part which derives fDIV from fASC The baudrate timer part which generates the sample clock fBRT and the baudrate clock fBR Prior to an Autobaud Detection the prescaler part has to be set up by the CPU while the baudrate timer (register ASCx_BG) is initialized with a 13-bit value (BR_VALUE) automatically after a successful autobaud detection. For the following calculations, the fractional divider is used (FDE = 1). Note: It is also possible to use the fixed divide-by-2 or divide-by-3 prescaler. But the fractional divider allows the much more precise adaption of fDIV to the required value. Standard Baudrates For standard baudrate detection the baudrates as shown in Table 19-8 can be e.g. detected. Therefore, the output frequency fDIV of the baudrate generator must be set to a frequency derived from the module clock fASC in a way that it is equal to 11.0592 MHz. The value to be written into register FDV is the nearest integer value which is calculated according the following formula: 512 x 11.0592 MHz FDV = --------------------------------------------------(19.1) f ASC Table 19-8 defines the nine standard baudrates (Br0 - Br8) which can be detected for fDIV = 11.0592 MHz. Table 19-8 Baudrate Numbering Br0 Br1 Br2 Br3 Br4 Br5 Br6 Br7 Br8 User's Manual ASC_X8, V2.1 Autobaud Detection Using Standard Baudrates (fDIV = 11.0592 MHz) Detectable Standard Baudrate 230.400 kbit/s 115.200 kbit/s 57.600 kbit/s 38.400 kbit/s 19.200 kbit/s 9600 bit/s 4800 bit/s 2400 bit/s 1200 bit/s Divide Factor df 48 96 192 288 576 1152 2304 4608 9216 19-30 BG is Loaded after Detection with Value 2 = 002H 5 = 005H 11 = 00BH 17 = 011H 35 = 023H 71 = 047H 143 = 08FH 287 = 11FH 575 = 23FH V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) According to Table 19-8 a baudrate of 9600 bit/s is achieved when register ASCx_BG is loaded with a value of 047H, assuming that fDIV has been set to 11.0592 MHz. Table 19-8 also lists a divide factor df which is defined with the following formula: DIV Baudrate = -------df f (19.2) This divide factor df defines a fixed relationship between the prescaler output frequency fDIV and the baudrate to be detected during the Autobaud Detection operation. This means, changing fDIV results in a totally different baudrate table in means of baudrate values. For the baudrates to be detected, the following relations are always valid: Br0 = fDIV/48D, Br1 = fDIV/96D, ... up to Br8 = fDIV/9216D A requirement for detecting standard baudrates up to 230.400 kbit/s is the fDIV minimum value of 11.0592 MHz. With the value FD_VALUE the fractional divider fDIV is adapted to the module clock frequency fASC. Table 19-9 defines the deviation of the standard baudrates when using autobaud detection depending on the module clock fASC. Table 19-9 Standard Baudrates - Deviations and Errors for Autobaud Detection FDV 472 436 354 315 307 283 236 226 189 172 142 Error in fDIV not possible +0.03% +0.1% +0.03% +0.14% -0.07% -0.04% +0.03% -0.22% +0.14% +0.24% +0.31% fASC 10 MHz 12 MHz 13 MHz 16 MHz 18 MHz 18.432 MHz 20 MHz 24 MHz 25 MHz 30 MHz 33 MHz 40 MHz Note: If the deviation of the baudrate after autobaud detection is to high, the baudrate generator (fractional divider FDV and reload register ASCx_BG) can be reprogrammed if required to get a more precise baudrate with less error. User's Manual ASC_X8, V2.1 19-31 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Non-Standard Baudrates Due to the relationship between Br0 to Br8 in Table 19-8 concerning the divide factor df other baudrates than the standard baudrates can be also selected. E.g. if a baudrate of 50 kbit/s has to be detected, Br2 is e.g. defined as baudrate for the 50 kbit/s selection. This further results in: fDIV = 50 kbit/s x df@Br2 = 50 kbit/s x 192 = 9.6 MHz Therefore, depending on the module clock frequency fASC, the value of the fractional divider (register FDV) must be set in this example according to the formula: 512 x f DIV FDV = -----------------------with fDIV = 9.6 MHz (19.3) f ASC Using this selection (fDIV = 9.6 MHz), the detectable baudrates start at 200 kbit/s (Br0) down to 1042 bit/s (Br8). Table 19-10 shows the baudrate table for this example. Table 19-10 Autobaud Detection Using Non-Standard Baudrates (fDIV = 9.6 MHz) Baudrate Numbering Br0 Br1 Br2 Br3 Br4 Br5 Br6 Br7 Br8 Detectable NonStandard Baudrates 200.000 kbit/s 100.000 kbit/s 50 kbit/s 33.333 kbit/s 16.667 kbit/s 8333 bit/s 4167 bit/s 2083 bit/s 1047 bit/s Divide Factor df 48 96 192 288 576 1152 2304 4608 9216 BG is Loaded after Detection with Value 2 = 002H 5 = 005H 11 = 00BH 17 = 011H 35 = 023H 71 = 047H 143 = 08FH 287 = 11FH 575 = 23FH User's Manual ASC_X8, V2.1 19-32 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.5.4 Overwriting Registers on Successful Autobaud Detection With a successful Autobaud Detection some bits in registers ASCx_CON and ASCx_BG are automatically set to a value which corresponds to the mode and baudrate of the detected serial frame conditions (see Table 19-11). In control register ASCx_CON the mode control bits M and the parity select bit ODD are overwritten. Register ASCx_BG is loaded with the 13-bit reload value for the baudrate timer. Table 19-11 Autobaud Detection Overwrite Values for the CON Register Detected Parameters Operating Mode 7 bit, even parity 7 bit, odd parity 8 bit, even parity 8 bit, odd parity 8 bit, no parity Br0 Br1 Br2 Br3 Br4 Br5 Br6 Br7 Br8 M 011 011 111 111 001 - ODD 0 1 0 1 0 - BR_VALUE - Baudrate 2 = 002H 5 = 005H 11 = 00BH 17 = 011H 35 = 023H 71 = 047H 143 = 08FH 287 = 11FH 575 = 23FH Note: The autobaud detection interrupts are described in Section 19.7. User's Manual ASC_X8, V2.1 19-33 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.6 Hardware Error Detection Capabilities To improve the safety of serial data exchange, the serial channel ASC provides an error interrupt request flag to indicate the presence of an error, and three (selectable) error status flags in register ASCx_CON to indicate which error has been detected during reception. Upon completion of a reception, the error interrupt request line EIR will be activated simultaneously with the receive interrupt request line RIR, if one or more of the following conditions are met: * If the framing error detection enable bit FEN is set and any of the expected stop bits is not high, the framing error flag FE is set, indicating that the error interrupt request is due to a framing error (Asynchronous Mode only). If the parity error detection enable bit PEN is set in the modes where a parity bit is received, and the parity check on the received data bits proves false, the parity error flag PE is set, indicating that the error interrupt request is due to a parity error (Asynchronous Mode only). If the overrun error detection enable bit OEN is set and the last character received was not read out of the receive buffer by software or by a DMA transfer at the time the reception of a new frame is complete, the overrun error flag OE is set indicating that the error interrupt request is due to an overrun error (Asynchronous and Synchronous Mode). * * User's Manual ASC_X8, V2.1 19-34 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.7 Interrupts Six interrupt sources are provided for serial channel ASC. Line TIR indicates a transmit interrupt, TBIR indicates a transmit buffer interrupt, RIR indicates a receive interrupt and EIR indicates an error interrupt of the serial channel. The autobaud detection unit provides two additional interrupts, the ABSTIR start of autobaud operation interrupt and the ABDETIR autobaud detected interrupt. The interrupt output lines TBIR, TIR, RIR, EIR, ABSTIR, and ABDETIR are activated (active state) for two periods of the module clock fASC. The cause of an error interrupt request (framing, parity, overrun error) can be identified by the error status flags FE, PE, and OE. For the two autobaud detection interrupts register ABSTAT provides status information. Note: In contrary to the error interrupt request line EIR, the error status flags FE/PE/OE are not reset automatically but must be cleared by software. For normal operation (i.e. besides the error interrupt) the ASC provides three interrupt requests to control data exchange via this serial channel: * * * TBIR is activated when data is moved from TBUF to the transmit shift register. TIR is activated before the last bit of an asynchronous frame is transmitted, or after the last bit of a synchronous frame has been transmitted. RIR is activated when the received frame is moved to RBUF. Note: While the receive task is handled by a single interrupt handler, the transmitter is serviced by two interrupt handlers. This provides advantages for the servicing software. For single transfers it is sufficient to use the transmitter interrupt (TIR), which indicates that the previously loaded data has been transmitted, except for the last bit of an asynchronous frame. For multiple back-to-back transfers it is necessary to load the following piece of data at last until the time the last bit of the previous frame has been transmitted. In Asynchronous Mode this leaves just one bit-time for the handler to respond to the transmitter interrupt request, in Synchronous Mode it is impossible at all. Using the transmit buffer interrupt (TBIR) to reload transmit data gives the time to transmit a complete frame for the service routine, as TBUF may be reloaded while the previous data is still being transmitted. The start of autobaud operation interrupt ABSTIR is generated whenever the autobaud detection unit is enabled (ABEN and ABDETEN and ABSTEN are set), and a start bit has been detected at RxD. In this case ABSTIR is generated during Autobaud Detection whenever a start bit is detected. The autobaud detected interrupt ABDETIR is always generated after recognition of the second character of the two-byte frame, this means after a successful Autobaud Detection. If FCDETEN is set the autobaud detected interrupt ABDETIR is also generated after the recognition of the first character of the two-byte frame. User's Manual ASC_X8, V2.1 19-35 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Asynchronous Mode TIR TBIR Start Stop TBIR Start Stop TIR TBIR Start Stop ABDETIR Start Stop TIR Idle Idle RIR Synchronous Mode TIR TBIR TBIR RIR RIR TIR TBIR TIR Idle Idle RIR Asynchronous Modes Autobaud Detection ABSTIR Start ABDETIR 1) Stop RIR RIR Idle 1. Character 2. Character 1) Only if FCDETEN = 1 MCT05450 Figure 19-19 ASC Interrupt Generation As shown in Figure 19-19, TBIR is an early trigger for the reload routine, while TIR indicates the completed transmission. Therefore, software using handshake should rely on TIR at the end of a data block to ensure that all data has actually been transmitted. The six interrupts of the ASC0 and of the ASC1 module are controlled by the following service request control registers: * * * * * ASC0_ABIC, ASC1_ABIC: control the autobaud interrupts ASC0_TIC, ASC1_TIC: control the transmit interrupts ASC0_RIC, ASC1_RIC: control the receive interrupts ASC0_EIC, ASC1_EIC: control the error interrupts ASC0_TBIC, ASC1_TBIC: control the transmit buffer empty interrupt Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual ASC_X8, V2.1 19-36 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) The two autobaud interrupt request lines (start of autobaud detection and end of autobaud detection) in each ASC module are `ORed' together; the `ORed' output signal is connected to the interrupt control register. This is shown in Figure 19-20. ASCx Kernel start_autobaud_detect_irq end_autobaud_detect_irq _ >1 ASCx_ABIC (x = 0 ... 1) MCA05451 Figure 19-20 Wiring of Autobaud Interrupts Table 19-12 summarizes all interrupt sources: Table 19-12 ASC Interrupt Sources Interrupt TBUF Action Signal TBIR Description A write action to the transmit shift register from the transmit buffer register ASCx_TBUF. If a FIFO is configured for the ASC and bit TXTMEN is cleared, TXFIFL defines when the interrupt is generated depending on the FIFO fill state. The interrupt is generated after the last (eight) data bit of a transmission frame is send via line TxD by the transmit shift register. Note: Only for Synchronous Mode Transmit Interrupt TIR The interrupt is generated just before the last bit of a transmission frame is send via line TxD by the transmit shift register. If a FIFO is configured for the ASC and bit XTMEN is cleared, TXFIFL defines when the interrupt is generated depending on the FIFO fill state. Note: Only for Asynchronous Modes Receive Interrupt RIR The interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register. Note: Only for Synchronous Mode Transmit Interrupt TIR User's Manual ASC_X8, V2.1 19-37 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 19-12 ASC Interrupt Sources (cont'd) Interrupt Receive Interrupt Signal RIR Description The interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register. If a FIFO is configured for the ASC and bit RXTMEN is cleared, RXFIFL defines when the interrupt is generated depending on the FIFO fill state. Note: Only for Asynchronous Modes Receive Error RIR and The interrupt is generated when the received frame is copied Interrupt EIR from the receive shift register to the receive buffer register and the receive buffer contains already valid data. Note: Only for Synchronous Mode Receive Overflow RIR and If an additional frame is received when the FIFO is completely EIR full an overflow error occurs. Both interrupts are generated and the previously received frame is overwritten in the FIFO and therefore lost. EIR RIR A read operation from the CPU to an empty receive FIFO generates this interrupt. In Transparent Mode a receive interrupt is always generated on a read operation from the CPU to the receive FIFO if the FIFO is not empty after this operation. A transmit buffer interrupt is generated when the transmit FIFO is flushed. A transmit buffer interrupt is generated when the transmit FIFO is enabled by setting bits TXTMEN and TXFEN when it was previously disabled in Transparent Mode. If an additional frame is written to the transmit FIFO when it is completely full an overflow error occurred. The interrupt is generated and the previously written frame is overwritten and therefor lost in the FIFO. Read to empty FIFO Transparent Read Operation Flush Action FIFO Enable TBIR TBIR Transmit Overflow EIR Frame Error Parity Error RIR and An expected stop bit is not high. EIR Note: Asynchronous Mode only RIR and When a parity bit is received that does not fit to the parity of EIR the received data. Note: Asynchronous Mode only User's Manual ASC_X8, V2.1 19-38 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.8 Registers Table 19-13 shows all registers which are required for programming the ASC modules. It summarizes the ASC kernel registers and the interrupt control registers and lists their addresses. Table 19-13 ASC Module Register Summary Name Description ASC0 Addresses 16-Bit ASCx_CON ASCx_TBUF ASCx_RBUF ASCx_ABCON ASCx_ABSTAT ASCx_BG ASCx_FDV ASCx_PMW ASCx_RXFCON ASCx_TXFCON ASCx_FSTAT ASCx_ABIC ASCx_TIC ASCx_RIC ASCx_EIC ASCx_TBIC Control Register Transmit Buffer Register Receive Buffer Register Autobaud Status Register Baudrate Timer Reload Register IrDA Pulse Mode and Width Register Receive FIFO Control Register Transmit FIFO Control Register FIFO Status Register 8-Bit SFR SFR SFR FFB0H D8H FEB0H 58H FEB2H 59H F0B8H 5CH FEB4H 5AH Reg. Area ASC1 Addresses 16-Bit 8-Bit FFB8H DCH FEB8H 5CH FEBAH 5DH Autobaud Control Register F1B8H DCH ESFR F1BCH DEH ESFR F0BCH 5EH SFR SFR SFR FEBCH 5EH FEBEH 5FH FEACH 56H 53H 52H Fractional Divider Register FEB6H 5BH FEAAH 55H F0C6H 63H F0C4H 62H F0BAH 5DH ESFR F0A6H ESFR F0A4H ESFR F0BEH 5FH ESFR F1BAH DDH SFR/ F182H ESFR SFR/ F18AH ESFR SFR/ F192H ESFR ESFR F150H C1H C5H C9H A8H Autobaud Interrupt Control F15CH AEH Register Transmit Interrupt Control Register Receive Interrupt Control Register Error Interrupt Control Register Transmit Buffer Interrupt Control Register FF6CH B6H FF6EH B7H FF70H B8H F19CH CEH User's Manual ASC_X8, V2.1 19-39 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Control Register The operating mode of the serial channel ASC is controlled by its control register CON. This register contains control bits for mode and error check selection, and status flags for error identification. ASCx_CON Control Register 15 R rw 14 13 12 11 10 SFR (Table 19-13) 9 FE rwh 8 7 6 5 4 Reset Value: 0000H 3 2 1 M rw 0 LB BRS ODD FDE OE rw rw rw rw rwh PE OEN FEN rwh rw rw PEN/ REN STP RxDI rw rwh rw Field R Bits 15 Type rw Description Baudrate Generator Run Control Bit 0 Baudrate generator disabled (ASC inactive) 1 Baudrate generator enabled Note: BR_VALUE should only be written if R = 0. Loopback Mode Enabled 0 Loopback Mode disabled. Standard transmit/receive Mode 1 Loopback Mode enabled Baudrate Selection 0 Baud rate timer prescaler divide-by-2 selected 1 Baud rate timer prescaler divide-by-3 selected Note: BRS is don't care if FDE = 1 (fractional divider selected). LB 14 rw BRS 13 rw ODD 12 rw Parity Selection 0 Even parity selected (parity bit of 1 is included in data stream on odd number of 1 and parity bit of 0 is included in data stream on even number of 1) 1 Odd parity selected (parity bit of 1 is included in data stream on even number of 1 and parity bit of 0 is included in data stream on odd number of 1) User's Manual ASC_X8, V2.1 19-40 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field FDE Bits 11 Type rw Description Fractional Divider Enable 0 Fractional divider disabled 1 Fractional divider enabled and used as prescaler for baudrate generator (bit BRS is don't care) Overrun Error Flag Set by hardware on an overrun/underflow error (OEN = 1). Must be cleared by software. Framing Error Flag Set by hardware on a framing error (FEN = 1). Must be cleared by software. Parity Error Flag Set by hardware on a parity error (PEN = 1). Must be cleared by software. Overrun Check Enable 0 Ignore overrun errors 1 Check overrun errors Framing Check Enable (Asynchronous Mode only) 0 Ignore framing errors 1 Check framing errors Parity Check Enable/RxDI Invert in IrDA Mode All Asynchronous Modes without IrDA Mode (PEN): 0 Ignore parity 1 Check parity Only in IrDA Mode (RxDI): 0 RxD input is not inverted 1 RxD input is inverted Receiver Enable Bit 0 Receiver disabled 1 Receiver enabled Note: REN is cleared by hardware after reception of a byte in synchronous mode. STP 3 rw Number of Stop Bits Selection 0 One stop bit 1 Two stop bits OE 10 rwh FE 9 rwh PE 8 rwh OEN 7 rw FEN 6 rw PEN / RxDI 5 rw REN 4 rwh User's Manual ASC_X8, V2.1 19-41 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field M Bits [2:0] Type rw Description Mode Control 000 8-bit-data for synchronous operation 001 8-bit-data for asynchronous operation 010 8-bit-data IrDA Mode for asynchronous operation 011 7-bit-data and parity for asynchronous operation 100 9-bit-data for asynchronous operation 101 8-bit-data and wake-up bit for asynchronous operation 110 Reserved. Do not use this combination 111 8-bit-data and parity for asynchronous operation Baudrate Register The ASC baudrate timer reload register BG contains the 13-bit reload value for the baudrate timer in Asynchronous and Synchronous Mode. ASCx_BG Baudrate Timer/Reload Reg. 15 14 13 12 11 10 SFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 BR_VALUE rw Field BR_VALUE Bits [12:0] Type rw Description Baudrate Timer/Reload Value Reading returns the 13-bit content of the baudrate timer; writing loads the baudrate timer/reload value. Note: BG should only be written if R = 0. User's Manual ASC_X8, V2.1 19-42 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Fractional Divider Register The ASC fractional divider register FDV contains the 9-bit divider value for the fractional divider (Asynchronous Mode only). It is also used for reference clock generation of the autobaud detection unit. ASCx_FDV Fractional Divider Register 15 14 13 12 11 10 SFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 FD_VALUE rw Field FD_VALUE Bits [8:0] Type rw Description Fractional Divider Register Value FD_VALUE contains the 9-bit value of the fractional divider which defines the fractional divider ratio n/512 (n = 0 ... 511). With n = 0, the fractional divider is switched off (input = output frequency, fDIV = fASC, see Figure 19-14). User's Manual ASC_X8, V2.1 19-43 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) IrDA Pulse Mode/Width Register The ASC IrDA pulse mode and width register PMW contains the 8-bit IrDA pulse width value and the IrDA pulse width mode select bit. This register is only required in the IrDA operating mode. ASCx_PMW IrDA Pulse Mode/Width Reg. 15 14 13 12 11 10 SFR (Table 19-13) 9 8 IRP W rw 7 6 5 4 Reset Value: 0000H 3 2 1 0 PW_VALUE rw Field IRPW Bits 8 Type rw Description IrDA Pulse Width Selection 0 IrDA pulse width is 3/16 bit time 1 IrDA pulse width is defined by PW_VALUE IrDA Pulse Width Value PW_VALUE is the 8-bit value n, which defines the variable pulse width of an IrDA pulse. Depending on the ASC input frequency fASC, this value can be used to adjust the IrDA pulse width to value which is not equal 3/16 bit time (e.g. 1.6 ms). PW_VALUE [7:0] rw User's Manual ASC_X8, V2.1 19-44 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Transmitter Buffer Register The ASC transmitter buffer register TBUF contains the transmit data value in Asynchronous and Synchronous Mode. ASCx_TBUF Transmit Buffer Register 15 14 13 12 11 10 SFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 TD_VALUE rw Field TD_VALUE Bits [8:0] Type rw Description Transmit Data Register Value TBUF contains the data to be transmitted in asynchronous and synchronous operating mode of the ASC. Data transmission is double buffered. Therefore, a new value can be written to TBUF before the transmission of the previous value is complete. User's Manual ASC_X8, V2.1 19-45 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Receiver Buffer Register The ASC Receiver buffer register RBUF contains the transmit data value in Asynchronous and Synchronous Modes. ASCx_RBUF Receive Buffer Register 15 14 13 12 11 10 SFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 RD_VALUE rw Field RD_VALUE Bits [8:0] Type rw Description Receive Data Register Value RBUF contains the received data bits and, depending on the selected mode, the parity bit in asynchronous and synchronous operating mode of the ASC. In asynchronous operating mode with M = 011 (7-bit data + parity) the received parity bit is written into RD7. In asynchronous operating mode with M = 111 (8-bit data + parity) the received parity bit is written into RD8. User's Manual ASC_X8, V2.1 19-46 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Autobaud Control Register The autobaud control register ABCON of the ASC module is used to control the autobaud detection operation. It contains its general enable bit, the interrupt enable control bits, and data path control bits. ASCx_ABCON Autobaud Control Register 15 14 13 12 11 RX INV rw 10 TX INV rw ESFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 ABEM rw FC AB ABS AUR AB DET DET T EN EN EN EN EN rw rw rw rw rwh Field RXINV Bits 11 Type rw Description Receive Inverter Enable 0 Receive inverter disabled 1 Receive inverter enabled Transmit Inverter Enable 0 Transmit inverter disabled 1 Transmit inverter enabled Autobaud Echo Mode Enable In Echo Mode the serial data at RxD is switched to TxD output. 00 Echo Mode disabled 01 Echo Mode is enabled during Autobaud Detection 10 Echo Mode is always enabled 11 Reserved; do not use this combination First Character of Two-Byte Frame Detected Enable 0 Autobaud Detection interrupt ABDETIR becomes active after the two-byte frame recognition 1 Autobaud Detection interrupt ABDETIR becomes active after detection of the first and second byte of the two-byte frame Autobaud Detection Interrupt Enable 0 Autobaud Detection interrupt disabled 1 Autobaud Detection interrupt enabled TXINV 10 rw ABEM [9:8] rw FCDETEN 4 rw ABDETEN 3 rw User's Manual ASC_X8, V2.1 19-47 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field ABSTEN Bits 2 Type rw Description Start of Autobaud Detection Interrupt Enable 0 Start of Autobaud Detection interrupt disabled 1 Start of Autobaud Detection interrupt enabled Automatic Autobaud Control of CON.REN 0 CON.REN is not affected during autobaud detection 1 CON.REN is cleared (receiver disabled) when ABEN and AUREN are set together. CON.REN is set (receiver enabled) after a successful Autobaud Detection (with the stop bit detection of the second character) Autobaud Detection Enable 0 Autobaud detection is disabled 1 Autobaud detection is enabled Note: ABEN is reset by hardware after a successful Autobaud Detection; (with the stop bit detection of the second character). Resetting ABEN by software if it was set aborts the Autobaud Detection. AUREN 1 rw ABEN 0 rwh User's Manual ASC_X8, V2.1 19-48 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Autobaud Status Register The autobaud status register ABSTAT of the ASC module indicates the status of the autobaud detection operation. ASCx_ABSTAT Autobaud Status Register 15 14 13 12 11 10 - ESFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DET SCC SCS FCC FCS WA DET DET DET DET IT rwh rwh rwh rwh rwh Field DETWAIT Bits 4 Type rwh Description Autobaud Detection is Waiting 0 Either character `a', `A', `t', or `T' has been detected 1 The autobaud detection unit waits for the first `a' or `A' Bit is cleared when either FCSDET or FCCDET is set (`a' or `A' detected). Bit can be also cleared by software. DETWAIT is set by hardware when ABEN is set. Second Character with Capital Letter Detected 0 No capital `T' character detected 1 Capital `T' character detected Bit is cleared by hardware when ABEN is set or if FCSDET or FCCDET or SCSDET is set. Bit can be also cleared by software. Second Character with Small Letter Detected 0 No small `t' character detected 1 Small `t' character detected Bit is cleared by hardware when ABEN is set or if FCSDET or FCCDET or SCCDET is set. Bit can be also cleared by software. SCCDET 3 rwh SCSDET 2 rwh User's Manual ASC_X8, V2.1 19-49 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field FCCDET Bits 1 Type rwh Description First Character with Capital Letter Detected 0 No capital `A' character detected 1 Capital `A' character detected Bit is cleared by hardware when ABEN is set or if FCSDET or SCSDET or SCCDET is set. Bit can be also cleared by software. First Character with Small Letter Detected 0 No small `a' character detected 1 Small `a' character detected Bit is cleared by hardware when ABEN is set or if FCCDET or SCSDET or SCCDET is set. Bit can be also cleared by software. FCSDET 0 rwh Note: SCSDET or SCCDET are set when the second character has been recognized. ABEN is reset and ABDETIR set after SCSDET or SCCDET have been set. User's Manual ASC_X8, V2.1 19-50 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Receive FIFO Control Register ASCx_RXFCON Receive FIFO Control Reg. 15 14 13 12 11 10 ESFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0100H 3 2 1 0 RXFITL rw RX RXF RXF TM FLU EN EN rw rw rw Field RXFITL Bits [11:8] Type rw Description Receive FIFO Interrupt Trigger Level Defines a receive FIFO interrupt trigger level. A receive interrupt request (RIR) is generated after the reception of a byte when the filling level of the receive FIFO is equal to or greater than RXFITL. 0000 Reserved. Do not use this combination 0001 Interrupt trigger level is set to one 0010 Interrupt trigger level is set to two ... ... 0111 Interrupt trigger level is set to seven 1000 Interrupt trigger level is set to eight Note: In Transparent Mode this bitfield is don't care. Note: Combinations defining an interrupt trigger level greater than the FIFO size should not be used. RXTMEN 2 rw Receive FIFO Transparent Mode Enable 0 Receive FIFO Transparent Mode is disabled 1 Receive FIFO Transparent Mode is enabled Note: This bit is don't care if the receive FIFO is disabled (RXFEN = 0). User's Manual ASC_X8, V2.1 19-51 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field RXFFLU Bits 1 Type rw Description Receive FIFO Flush 0 No operation 1 Receive FIFO is flushed Note: Setting RXFFLU clears bitfield RXFFL in register FSTAT. RXFFLU is always read as 0. RXFEN 0 rw Receive FIFO Enable 0 Receive FIFO is disabled 1 Receive FIFO is enabled Note: Resetting RXFEN automatically flushes the receive FIFO. Note: After a successful autobaud detection sequence, the RXFIFO should be flushed before data is received. User's Manual ASC_X8, V2.1 19-52 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Transmit FIFO Control Register ASCx_TXFCON Transmit FIFO Control Reg. 15 14 13 12 11 10 ESFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0100H 3 2 TX TM EN rw 1 0 TXFITL rw TXF TXF FLU EN rw rw Field TXFITL Bits [11:8] Type rw Description Transmit FIFO Interrupt Trigger Level Defines a transmit FIFO interrupt trigger level. A transmit interrupt request (TIR) is generated after the transfer of a byte when the filling level of the transmit FIFO is equal to or lower than TXFITL. 0000 Reserved. Do not use this combination 0001 Interrupt trigger level is set to one 0010 Interrupt trigger level is set to two ... ... 0111 Interrupt trigger level is set to seven 1000 Interrupt trigger level is set to eight Note: In Transparent Mode this bitfield is don't care. Note: Combinations defining an interrupt trigger level greater than the FIFO size should not be used. TXTMEN 2 rw Transmit FIFO Transparent Mode Enable 0 Transmit FIFO Transparent Mode is disabled 1 Transmit FIFO Transparent Mode is enabled Note: This bit is don't care if the receive FIFO is disabled (TXFEN = 0). User's Manual ASC_X8, V2.1 19-53 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field TXFFLU Bits 1 Type rw Description Transmit FIFO Flush 0 No operation 1 Transmit FIFO is flushed Note: Setting TXFFLU clears bitfield TXFFL in register ASCx_FSTAT. TXFFLU is always read as 0. TXFEN 0 rw Transmit FIFO Enable 0 Transmit FIFO is disabled 1 Transmit FIFO is enabled Note: Resetting TXFEN automatically flushes the transmit FIFO. User's Manual ASC_X8, V2.1 19-54 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) FIFO Status Register ASCx_FSTAT FIFO Status Register 15 14 13 12 11 10 ESFR (Table 19-13) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 TXFFL rh RXFFL rh Field TXFFL Bits [11:8] Type rh Description Transmit FIFO Filling Level 0000 Transmit FIFO is filled with zero bytes 0001 Transmit FIFO is filled with one byte ... ... 0111 Transmit FIFO is filled with seven bytes 1000 Transmit FIFO is filled with eight bytes Note: TXFFL is cleared after a receive FIFO flush operation. RXFFL [3:0] rh Receive FIFO Filling Level 0000 Receive FIFO is filled with zero bytes 0001 Receive FIFO is filled with one byte ... ... 0111 Receive FIFO is filled with seven bytes 1000 Receive FIFO is filled with eight bytes Note: RXFFL is cleared after a receive FIFO flush operation. User's Manual ASC_X8, V2.1 19-55 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 19.9 Interfaces of the ASC Modules In the XC167 the ASC modules are connected to IO ports and other internal modules according to Figure 19-21 and Figure 19-22. The input/output lines of ASC0 and ASC1 are connected to pins of Ports P3. The 6 interrupt request lines of each module are connected to the Interrupt Control Block. Clock control and emulation control of the SSC Module is handled by the System Control Unit, SCU. System Control Unit (SCU) fASC ASC0DIS S0RxD S0TIRQ S0RIRQ ASC0 Module S0TxD Port P3 Control P3.10/TxDA0 P3.11/RxDA0 Interrupt Control Block S0EIRQ S0TBIRQ S0ABIRQ1 S0ABIRQ2 MCA05452 Figure 19-21 ASC0 Module Interfaces System Control Unit (SCU) fASC ASC1DIS S1RxD S1TIRQ S1RIRQ ASC1 Module S1TxD Port P3 Control P3.0/TxDA1 P3.1/RxDA1 Interrupt Control Block S1EIRQ S1TBIRQ S1ABIRQ1 S1ABIRQ2 MCA05453 Figure 19-22 ASC1 Module Interfaces User's Manual ASC_X8, V2.1 19-56 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Note: In synchronous operating mode, the direction of the RxD pin is not automatically set by the ASC modules; it must be switched by software via the corresponding bit in register DP3, depending on the selected mode (receive or transmit data). Note: To select RxDA1 as alternate output function for P3.1, it is sufficient to set bit 1 of register ALTSEL0P3, the corresponding bit in register ALTSEL1P3 is "don't care". User's Manual ASC_X8, V2.1 19-57 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 20 High-Speed Synchronous Serial Interface (SSC) The XC167 contains two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1. The following sections present the general features and operations of such an SSC module. The final section describes the actual implementation of the two SSC modules including their interconnections with other on-chip modules. 20.1 Introduction The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and halfduplex serial synchronous communication up to 20 Mbit/s (@ 40 MHz module clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity, and phase are programmable. This supports communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit baudrate generator provides the SSC with a separate serial clock signal. Features and Functions * * Master and Slave Mode operation - Full-duplex or half-duplex operation Flexible data format - Programmable number of data bits: 2 to 16 bits - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock Baudrate generation from 20 Mbit/s to 306.6 bit/s (@ 40 MHz module clock) Interrupt generation - On a Transmitter-Empty condition - On a Receiver-Full condition - On an Error condition (receive, phase, baudrate, transmit error) * * 20.2 Operational Overview The high-speed synchronous serial interface can be configured in a very flexible way, so it can be used with other synchronous serial interfaces, can serve for master/slave or multimaster interconnections or can operate compatible with the popular SPI interface. Thus, the SSC can be used to communicate with shift registers (IO expansion), peripherals (e.g. EEPROMs, etc.) or other controllers (networking). The SSC supports half-duplex and full-duplex communication. Data is transmitted on lines MTX/STX or received on lines MRX/SRX, connected with pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line User's Manual SSC_X, V2.0 20-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) MSCLK (Master Serial Shift Clock) or input via line SSCLK (Slave Serial Shift Clock). Both lines are connected to pin SCLK. These pins are alternate functions of port pins. A block diagram of the SSC Module is shown in Figure 20-2. From the programmer's point of view, the term `SSC unit' refers to a set of registers (see Figure 20-1) which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and including their direction control bits. Data Registers TB RB Control Registers CON BR Interrupt Registers TIC RIC EIC System Registers SSC0 P3 DP3 ALTSEL0P3 P1H DP1H ALTSEL0P1H SYSCON3 OPSEN TB / RB CON BR TIC / RIC / EIC Py DPy ALTSEL0Py SYSCON3 Transmit / Receive Buffer Register SSC Control Register Baudrate Timer / Reload Register Transmit / Receive / Error Interrupt Control Register Port Py Data Register (y = 1H, 3) Port Py Direction Control Register (y = 1H, 3) Port Py Alternate Output Select Register 0 (y = 1H, 3) SCU System Control Register 3 MCA05454 Figure 20-1 SFRs Associated with the SSC Unit User's Manual SSC_X, V2.0 20-2 V2.0, 2004-04 SSC1 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) fSSC Baudrate Generator Clock Control MSCLK SSCLK to Pin SCLK TIRQ SSC Control Block RIRQ EIRQ Transmit Interrupt Receive Interrupt Request Error Interrupt Request MTX Status Control Input/ Output Line Control MRX STX SRX to Pin MTSR to Pin MRST 16-bit Shift Register 16-bit Shift Register 16-bit Shift Register MCB05455 Figure 20-2 Synchronous Serial Channel (SSC) Block Diagram 20.2.1 Operating Mode Selection The operating mode of the SSC module is controlled by its control register SSCx_CON. This register has a double function: * * During programming (SSC disabled by SSCx_CON.EN = 0), it provides access to a set of control bits During operation (SSC enabled by SSCx_CON.EN = 1), it provides access to a set of status flags In the following, the layout of register CON is shown for both functions. User's Manual SSC_X, V2.0 20-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) SSC Control Register (SSCx_CON.EN = 0: Programming Mode) SSCx_CON SSC Control Register 15 EN =0 rw 14 MS rw 13 12 11 10 SFR (Table 20-2) 9 8 7 LB rw 6 PO rw 5 PH rw 4 HB rw Reset Value: 0000H 3 2 BM rw 1 0 A BEN PEN REN TEN REN rw rw rw rw rw Field EN Bits 15 Type rw Description Enable Bit = 0 Transmission and reception disabled. Access to control bits. Master Select 0 Slave Mode. Operate on shift clock received via SCLK. 1 Master Mode. Generate shift clock and output it via SCLK. Automatic Reset Enable 0 No additional action upon a baudrate error 1 The SSC is automatically reset upon a baudrate error Baudrate Error Enable 0 Ignore baudrate errors 1 Check baudrate errors Phase Error Enable 0 Ignore phase errors 1 Check phase errors Receive Error Enable 0 Ignore receive errors 1 Check receive errors Transmit Error Enable 0 Ignore transmit errors 1 Check transmit errors Loop Back Control 0 Normal output 1 Receive input is connected with transmit output (half-duplex mode) MS 14 rw AREN 12 rw BEN 11 rw PEN 10 rw REN 9 rw TEN 8 rw LB 7 rw User's Manual SSC_X, V2.0 20-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Field PO Bits 6 Type rw Description Clock Polarity Control 0 Idle clock line is low, leading clock edge is lowto-high transition. 1 Idle clock line is high, leading clock edge is high-to-low transition. Clock Phase Control 0 Shift transmit data on the leading clock edge, latch on trailing edge. 1 Latch receive data on leading clock edge, shift on trailing edge. Heading Control 0 Transmit/Receive LSB First 1 Transmit/Receive MSB First Data Width Selection 0000 Reserved. Do not use this combination. 0001 Transfer Data Width is 2 bits ... Transfer Data Width is ( PH 5 rw HB 4 rw BM [3:0] rw SSC Control Register (SSCx_CON.EN = 1: Operating Mode) SSCx_CON SSC Control Register 15 EN =1 rw 14 MS rw 13 12 11 10 PE rwh SFR (Table 20-2) 9 RE rwh 8 TE rwh 7 6 5 4 - Reset Value: 0000H 3 2 BC rw 1 0 BSY BE rh rwh Field EN Bits 15 Type rw Description Enable Bit = 1 Transmission and reception enabled. Access to status flags and M/S control. Master/Slave Selection 0 Slave Mode. Operate on shift clock received via SCLK. 1 Master Mode. Generate shift clock and output it via SCLK. MS 14 rw User's Manual SSC_X, V2.0 20-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Field BSY BE Bits 12 11 Type rh rwh Description Busy Flag Set while a transfer is in progress. Do not write to!!! Baudrate Error Flag 0 No error 1 More than factor 2 or 0.5 between slave's actual and expected baudrate Phase Error Flag 0 No error 1 The received data has changed around sampling clock edge Receive Error Flag 0 No error 1 A reception was completed before the receive buffer was read Transmit Error Flag 0 No error 1 A transfer has started with the slave's transmit buffer not being updated Bit Count Field Shift counter is updated with every shifted bit. Do not write to!!! PE 19 rwh RE 9 rwh TE 8 rwh BC [3:0] rh Note: The target of an access to SSCx_CON (control bits or flags) is determined by the state of bit EN prior to the access; that is, writing C057H to SSCx_CON in programming mode (EN = 0) will initialize the SSC (EN was 0) and then turn it on (EN = 1). When writing to SSCx_CON, ensure that reserved locations receive zeros. Transmitter Buffer Register The SSC Transmit Buffer Register SSCx_TB (see Table 20-2) contains the transmit data value. Unselected bits of SSCx_TB are ignored during transmission. The transmit value must be right-aligned regardless of MSB or LSB first operation. Receiver Buffer Register The SSC Receive Buffer Register SSCx_RB (see Table 20-2) contains the receive data value. Unselected bits of SSCx_RB will be not valid and should be ignored. The received value is always right-aligned regardless of MSB or LSB first operation. User's Manual SSC_X, V2.0 20-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) The shift register of the SSC is connected to both, the transmit lines and the receive lines via the pin control logic (see block diagram in Figure 20-2). Transmission and reception of serial data are synchronized and take place at the same time, i.e. the same number of transmitted bits is also received. To prepare for a transfer, the transmit data is written into the Transmit Buffer (SSCx_TB) by software. It is moved to the shift register as soon as this is empty. An SSC master (CON.MS = 1) immediately begins transmitting, while an SSC slave (CON.MS = 0) will wait for an active shift clock. When the transfer starts, the busy flag CON.BSY is set and the Transmit Interrupt Request line TIRQ will be activated to indicate that register SSCx_TB may be reloaded again. When the programmed number of bits (2 ... 16) has been transferred, the contents of the shift register are moved to the Receive Buffer SSCx_RB and the Receive Interrupt Request line RIRQ is activated. If no further transfer is to take place (SSCx_TB is empty), CON.BSY will be cleared at the same time. Software should not modify CON.BSY, as this flag is hardware controlled. Note: Only one SSC can be master at a given time in a serial system. The transfer of serial data bits can be programmed in many respects: * * * * * * The data width can be specified from 2 bits to 16 bits A transfer may start with either the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading edge or the trailing edge of the shift clock signal The baudrate may be set from 306.6 bit/s up to 20 Mbit/s (@ 40 MHz module clock) The shift clock can be generated (MSCLK) or can be received (SSCLK) These features allow the adaptation of the SSC to a wide range of applications in which serial data transfer is required. The Data Width Selection supports the transfer of frames of any data length, from 2-bit "characters" up to 16-bit "characters". Starting with the LSB (CON.HB = 0) enables communication with SSC devices in Synchronous Mode or with 8051-like serial interfaces, for example. Starting with the MSB (CON.HB = 1) enables operation compatible with the SPI interface. Regardless of the data width selected and whether the MSB or the LSB is transmitted first, the transfer data is always right-aligned in registers SSCx_TB and SSCx_RB, with the LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the internal shift register logic. The unselected bits of SSCx_TB are ignored; the unselected bits of SSCx_RB will not be valid and should be ignored by the receiver service routine. The Clock Control allows the adaptation of transmit and receive behavior of the SSC to a variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shift out transmit data, while the other shift clock edge is used to latch in receive data. Bit PH selects the leading edge or the trailing edge for each function. Bit PO selects the level of User's Manual SSC_X, V2.0 20-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) the shift clock line in the idle state. Thus, for an idle-high clock, the leading edge is a falling edge, a 1-to-0 transition (see Figure 20-3). CON. CON. PO PH 0 0 1 1 0 1 0 1 Shift Clock SCLK Pins MTSR/MRST First Bit Latch Data Shift Data MCT05456 Transmit Data Last Bit Figure 20-3 Serial Clock Phase and Polarity Options 20.2.2 Full-Duplex Operation In a Full-Duplex serial configuration, illustrated in Figure 20-4, the various devices are connected via three lines. The definition of these lines is always determined by the master: The line connected to the master's data output line MTSR is the transmit line; the receive line is connected to its data input line MRST; the shift clock line is SCLK. Only the device selected for master operation generates and outputs the shift clock on line SCLK. All slaves receive this clock; thus, their SCLK pin must be switched to input mode. The output of the master's shift register is connected to the external transmit line, which in turn is connected to the slaves' shift register inputs. The outputs of the slaves' shift register are connected to the external receive line in order to enable the master to receive the data shifted out of the slaves. The external connections are hard-wired, the function and direction of these pins is determined by the master or slave operation of the individual device. Note: The shift direction shown in Figure 20-4 applies for MSB-first operation as well as for LSB-first operation. When initializing the devices in this configuration, one device must be selected for master operation while all other devices must be programmed for slave operation. Initialization includes the operating mode of the device's SSC and also the function of the respective port lines. User's Manual SSC_X, V2.0 20-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Master Shift Register MTSR Transmit MTSR Device #1 Device #2 Slave Shift Register MRST Receive MRST Clock SCLK Clock SCLK Clock Symbols Input Device #3 Slave Shift Register MTSR Push/Pull Output MRST Open-Drain Output SCLK Tri-Stated = Input MCA05457 Clock Figure 20-4 SSC Full-Duplex Configuration The data output pins MRST of all slave devices are connected together onto the one receive line in the configuration shown in Figure 20-4. During a transfer, each slave shifts out data from its shift register. There are two ways to avoid collisions on the receive line due to different slave data: * Only one slave drives the line, i.e. enables the driver of its MRST pin. All the other slaves must have their MRST pins programmed as input so only one slave can put its data onto the master's receive line. Only receiving data from the master is possible. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. The selected slave then switches its MRST line to output until it gets a de-selection signal or command. In the configuration depicted in Figure 20-4, Device #2 is the slave which has its output driver enabled as push/pull output. Device #3 is an inactive slave, it needs to disable its output driver by programming the pin to input mode. The slaves use their MRST outputs in open-drain mode. This forms a wired-AND connection. The receive line needs an external pull-up in this case. Corruption of the 20-9 V2.0, 2004-04 * User's Manual SSC_X, V2.0 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master only send ones (1). Because this high level is not actively driven onto the line, but only held through the pull-up device, the selected slave can pull this line actively to a low level when transmitting a zero bit. The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave. After performing the necessary initialization of the SSC, the serial interfaces can be enabled. For a master device, the clock line MSCLK will now go to its programmed polarity. The output data line MTX will go to either 0 or 1 until the first transfer will start. After a transfer, the data line MTX will always remain at the logic level of the last transmitted data bit. When the serial interfaces are enabled, the master device can initiate the first data transfer by writing the transmit data into register SSCx_TB. This value is copied into the shift register (assumed to be empty at this time), and the selected first bit of the transmit data will be placed onto the transmit line MTSR on the next clock from the baudrate generator (transmission starts only if bit EN = 1). Depending on the selected clock phase, a clock pulse will also be generated on the SCLK line. At the same time, with the opposite clock edge, the master latches and shifts in the data detected at its input line MRST. This "exchanges" the transmit data with the receive data. Because the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master's shift register, shifting out the data contained in the registers, and shifting in the data detected at the input line. After the preprogrammed number of clock pulses (via the data width selection), the data transmitted by the master is contained in all the slaves' shift registers, while the master's shift register holds the data of the selected slave. In the master and all slaves, the contents of the shift register are copied into the receive buffer SSCx_RB and the receive interrupt line RIRQ is activated. A slave device will immediately output the selected first bit (MSB or LSB of the transfer data) at line MRST when the contents of the transmit buffer are copied into the slave's shift register. Bit BSY is not set until the first clock edge at SCLK appears. The slave device will not wait for the next clock from the baudrate generator, as the master does. The reason for this is that, depending on the selected clock phase, the first clock edge generated by the master may already be used to clock in the first data bit. Thus, the slave's first data bit must already be valid at this time. Note: On the SSC, a transmission and a reception takes place at the same time, regardless of whether valid data has been transmitted or received. Note: The initialization of the CLK pin on the master requires some attention in order to avoid undesired clock transitions, which may disturb the other devices. Before the clock pin is switched to output via the related direction control register, the clock output level shall be selected in the control register SSCx_CON and the alternate output be prepared via the related ALTSEL register, or the output latch must be loaded with the clock idle level. User's Manual SSC_X, V2.0 20-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 20.2.3 Half-Duplex Operation In a Half-Duplex configuration, only one data line is necessary for both, receiving and transmitting of data. The data exchange line is connected to both, the MTSR and MRST pins of each device, the shift clock line is connected to the SCLK pin. The master device controls the data transfer by generating the shift clock, while the slave devices receive it. Due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. Similar to Full-Duplex mode, there are two ways to avoid collisions on the data exchange line: * * only the transmitting device may enable its transmit pin driver the non-transmitting devices use open-drain outputs and send only ones (1s). Because the data inputs and outputs are connected together, a transmitting device will clock in its own data at the input pin (MRST for a master device, MTSR for a slave). By this method, any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data. Master Shift Register MTSR MTSR Device #1 Transmit Device #2 Slave Shift Register MRST MRST Clock SCLK Clock SCLK Clock Symbols Input Device #3 Slave Shift Register MTSR Push/Pull Output MRST Open-Drain Output SCLK Tri-Stated = Input MCA05458 Clock Figure 20-5 SSC Half-Duplex Configuration User's Manual SSC_X, V2.0 20-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 20.2.4 Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer SSCx_TB is empty and ready to be loaded with the next transmit data. If SSCx_TB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay. On the data line, there is no gap between the two successive frames. For example, two 8-bit transfers would look the same as one 16-bit transfer. This feature can be used to interface with devices that can operate with or require more than 16 data bits per transfer. It is just a matter of software, how long a total data frame length can be. This option can also be used to interface to byte-wide and word-wide devices on the same serial bus, for instance. Note: Of course, this can happen only in multiples of the selected basic data width, because it would require disabling/enabling of the SSC to reprogram the basic data width on-the-fly. 20.2.5 Baudrate Generation The serial channel SSC has its own dedicated 16-bit Baudrate Generator with 16-bit reload capability, facilitating baudrate generation independent of the timers. Figure 20-6 shows the baudrate generator of the SSC in more detail. 16-bit Reload Register fSSC 2 16-bit Counter fSCLK fSCLKmax in Master Mode fSSC / 2 fSCLKmax in Slave Mode fSSC / 4 MCA05459 Figure 20-6 SSC Baudrate Generator The Baudrate Generator is clocked with the module clock fSSC. The counter counts downwards. Access to the Baudrate Generator is performed via one register, SSCx_BR, described below. User's Manual SSC_X, V2.0 20-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Baudrate Timer/Reload Register The SSC Baudrate Timer/Reload Register SSCx_BR has a double function. While the SSC is disabled, it serves as the reload register for the baudrate timer. Writing to it loads the timer reload register with the written reload value. Reading returns the current reload value. While the SSC is enabled, this register reflects the current baudrate timer contents. Writing to this register is not allowed while the SSC is enabled. Baudrate Calculation The timer is loaded with the reload value and starts counting immediately when the SSC is enabled. The formulas below calculate either the resulting baudrate for a given reload value, or the required reload value for a given baudrate: SSC Baudrate = -------------------------------------2 x ( + 1 ) f SSC BG = ----------------------------------- - 1 2 x Baudrate f (20.1) represents the contents of the reload register, taken as unsigned 16-bit integer; while baudrate is equal to fSCLK as shown in Figure 20-6. The maximum baudrate that can be achieved when using a module clock of 40 MHz is 20 Mbit/s in Master Mode (with = 0000H) or 10 Mbit/s in Slave Mode (with = 0001H). Table 20-1 lists some possible baudrates together with the required reload values and the resulting bit times, assuming a module clock of 40 MHz. Table 20-1 Reload Value 0000H 0001H 0009H 0013H 001AH 0027H 0063H 00C7H FFFFH Typical Baudrates of the SSC (fSSC = 40 MHz) Baudrate (= fSCLK) 20 Mbit/s (only in Master Mode) 10 Mbit/s 2 Mbit/s 1 Mbit/s 750 kbit/s 500 kbit/s 200 kbit/s 100 kbit/s 306.6 bit/s Deviation 0.0% 0.0% 0.0% 0.0% -1.25% 0.0% 0.0% 0.0% 0.0% User's Manual SSC_X, V2.0 20-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 20.2.6 Error Detection Mechanisms The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes; Transmit Error and Baudrate Error only apply to Slave Mode. When an error is detected, the respective error flag in register SSCx_CON is set and an error interrupt request will be generated by activating the EIRQ line (see Figure 20-7). The error interrupt handler may then check the error flags to determine the cause of the error interrupt. The error flags are not reset automatically but rather must be cleared by software after servicing. This allows servicing of some error conditions via interrupt, while the others may be polled by software. Note: The error interrupt handler must clear the associated (enabled) error flag(s) to prevent repeated interrupt requests. Bits in Register CON TEN Transmit Error TE REN Receive Error RE PEN Phase Error PE BEN Baudrate Error BE MCA05460 & & _ >1 Error Interrupt Request EIRQ & & Figure 20-7 SSC Error Interrupt Control A Receive Error (Master or Slave Mode) is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCx_RB. This condition sets the error flag RE and, when enabled via bit REN, the error interrupt request line EIRQ. The old data in the receive buffer SSCx_RB will be overwritten with the new value and is irretrievably lost. A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST (Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module User's Manual SSC_X, V2.0 20-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK. This condition sets the error flag PE and, when enabled via bit PEN, the error interrupt request line EIRQ. A Baudrate Error (Slave Mode) is detected when the incoming clock signal deviates from the programmed baudrate by more than 100%, i.e. it either is more than double or less than half the expected baudrate. This condition sets the error flag BE and, when enabled via bit BEN, the error interrupt request line EIRQ. Using this error detection capability requires that the slave's baudrate generator is programmed to the same baudrate as the master device. This feature detects false, additional or missing, pulses on the clock line (within a certain frame). Note: If this error condition occurs and bit AREN = 1, an automatic reset of the SSC will be performed in case of this error. This is done to re-initialize the SSC if too few or too many clock pulses have been detected. A Transmit Error (Slave Mode) is detected when a transfer was initiated by the master (SCLK gets active), but the transmit buffer SSCx_TB of the slave was not updated since the last transfer. This condition sets the error flag TE and, when enabled via bit TEN, the error interrupt request line EIRQ. If a transfer starts while the transmit buffer is not updated, the slave will shift out the `old' contents of the shift register, which usually is the data received during the last transfer. This may lead to corruption of the data on the transmit/receive line in half-duplex mode (open-drain configuration) if this slave is not selected for transmission. This mode requires that slaves not selected for transmission only shift out ones; that is, their transmit buffers must be loaded with FFFFH prior to any transfer. Note: A slave with push/pull output drivers not selected for transmission will usually have its output drivers switched off. However, in order to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer. The cause of an error interrupt request (receive, phase, baudrate, transmit error) can be identified by the error status flags in control register SSCx_CON. Note: The error status flags TE, RE, PE, and BE, are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software. User's Manual SSC_X, V2.0 20-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 20.2.7 Table 20-2 Name SSC Register Summary SSC Module Register Summary Description SSC0 Addresses 16-Bit 8-Bit SFR ESFR ESFR ESFR SFR/ ESFR SFR/ ESFR SFR/ ESFR FFB2H D9H F0B4H 5AH F0B0H 58H F0B2H 59H B9H BAH BBH Reg. Area SSC1 Addresses 16-Bit 8-Bit FF5EH AFH F05EH 2FH F05AH 2DH F05CH 2EH F1AAH D5H F1ACH D6H F1AEH D7H SSCx_CON SSCx_BR SSCx_TB SSCx_RB SSCx_TIC SSCx_RIC SSCx_EIC Control Register Baudrate Timer Reload Register Transmit Buffer Register Receive Buffer Register Transmit Interrupt Control FF72H Register Receive Interrupt Control Register Error Interrupt Control Register FF74H FF76H User's Manual SSC_X, V2.0 20-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 20.2.8 Port Configuration Requirements Table 20-3 shows the required register setting to configure the IO lines of the SSC modules for master or slave mode operation. Table 20-3 SSC0/SSC1 IO Selection and Setup Port Lines Alternate Select Register ALTSEL0P3.P8 = 1 ALTSEL0P3.P9 = 1 ALTSEL0P3.P13 = 1 ALTSEL0P3.P8 = 1 ALTSEL0P3.P9 = 1 ALTSEL0P3.P13 = 1 ALTSEL0P1H.P1 = 1 ALTSEL0P1H.P2 = 1 ALTSEL0P1H.P3 = 1 ALTSEL0P1H.P1 = 1 ALTSEL0P1H.P2 = 1 ALTSEL0P1H.P3 = 1 Direction and Port Output Register DP3.P8 = 0 DP3.P9 = 1 and P3.P9 = 1 IO Module Mode SSC0 Master P3.8 / MRST0 P3.9 / MTSR0 P3.13 / SCLK0 Slave P3.8 / MRST0 P3.9 / MTSR0 P3.13 / SCLK0 Input Output Output DP3.P13 = 1 and P3.P13 = 1 DP3.P8 = 1 and P3.P8 = 1 DP3.P9 = 0 DP3.P13 = 0 DP1H.P1 = 0 DP1H.P2 = 1 DP1H.P3 = 1 DP1H.P1 = 1 DP1H.P2 = 0 DP1H.P3 = 0 Output Input Input Input Output Output Output Input Input SSC1 Master P1H.1 / MRST1 P1H.2 / MTSR1 P1H.3 / SCLK1 Slave P1H.1 / MRST1 P1H.2 / MTSR1 P1H.3 / SCLK1 Note: The direction control bits in registers DP3 or DP1H must be set or cleared by software depending on the mode of operation selected (master or slave mode). They are not controlled automatically by the SSC modules. User's Manual SSC_X, V2.0 20-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 20.3 Interfaces of the SSC Modules In the XC167 the SSC modules are connected to IO ports and other internal modules according to Figure 20-8 and Figure 20-9. The input/output lines of SSC0 are connected to pins of Ports P3, while the input/output lines of SSC1 are connected to pins of Ports P1H. The three interrupt request lines of each module are connected to the Interrupt Control Block. Clock control and emulation control of the SSC Module is handled by the System Control Unit, SCU. System Control Unit (SCU) fSSC SSC0DIS SSC0 Module MTX MRX STX Port P3 Control P3.8/MRST0 SSC0_TIRQ Interrupt Control Block SSC0_RIRQ SSC0_EIRQ SRX MSCLK SSCLK P3.9/MTSR0 P3.13/SCLK0 MCA05461 Figure 20-8 SSC0 Module Interfaces System Control Unit (SCU) fSSC SSC1DIS SSC1 Module MTX MRX STX Port P1H Control P1H.1/MRST1 SSC1_TIRQ Interrupt Control Block SSC1_RIRQ SSC1_EIRQ SRX MSCLK SSCLK P1H.2/MTSR1 P1H.3/SCLK1 MCA05462 Figure 20-9 SSC1 Module Interfaces User's Manual SSC_X, V2.0 20-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21 IIC-Bus Module The IIC-Bus supports a defined protocol to enable devices to communicate directly with each other via a simple two-wire serial interface. One line is responsible for clock transfer and synchronization (SCL), the other is responsible for the data transfer (SDA). The on-chip IIC-Bus Module connects the XC167 to other external controllers and/or peripherals via the two-line serial IIC-Bus interface. The IIC-Bus Module provides communication at data rates of up to 400 kbit/s and features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to the IIC bus protocol. The module can operate in three different modes: Master mode, where the IIC-Bus Module controls the bus transactions and provides the clock signal. Slave mode, where an external master controls the bus transactions and provides the clock signal. Multimaster mode, where several masters can be connected to the bus, i.e. the IIC-Bus Module can be master or slave. The on-chip IIC-Bus Module allows efficient communication via the common IIC-Bus. The module unloads the CPU of low level tasks like * * * * * Serialization/De-serialization of bus data Generation of start and stop conditions Monitoring of the bus lines Evaluation of the device address in slave mode Bus access arbitration in multi-master mode Features * * * * * * Extended buffer allows up to 4 transmit/receive data bytes to be stored Selectable baudrate generation Support of standard 100 kbit/s and extended 400 kbit/s data rates Operation in 7-bit addressing or 10-bit addressing mode Flexible control via interrupt service routines or by polling Dynamic access to up to 3 physical IIC buses Applications * * * * * EEPROMs 7-Segment Displays Keyboard Controllers On-Screen Display Audio Processors User's Manual IIC_X, V2.0 21-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.1 Overview A block diagram of the XC167 IIC-Bus Module is shown in Figure 21-1, while Figure 21-2 illustrates a possible serial interface system. fIIC Baudrate Generator Module Control & Status Logic DIRQ Interrupt Request PIRQ Interrupt Request Receive/ Transmit Buffer Clock Line SCL Address Logic Shift Register IIC-Bus Driver & Monitor Pin Enable Lines Data Line SDA MCB05463 Figure 21-1 IIC-Bus Module Block Diagram The IIC-Bus Module has its own flexible Baudrate Generator. A 4-byte Receive/Transmit Buffer enables software to write or read longer message and eliminates the need to react after each received/transmitted byte. Serialization and de-serialization of the byte data is performed via an 8-bit Shift Register. The Address Logic analyzes the received slave address and informs the Control Logic when the device has been contacted by another station in the system. The Control and Status Logic controls the entire module and provides a number of status signals and flags, reflecting the conditions of the module to the software. To operate in an IIC-Bus system, it is not only necessary for a station to be able to drive the clock and data lines of the IIC-Bus, but also to monitor the actual levels on these lines and to detect special conditions, such as the start and stop conditions, and to perform clock synchronization as well as bus arbitration. This is handled by the IIC-Bus Driver and Monitor block. In addition, this block provides the port pin enable control for the three possible SCL/SDA signal pairs. Due to the feature that the IIC-Bus Module of the XC167 can control up to three SCL/SDA signal pairs, it is possible to build a system with separate IIC-buses as shown in Figure 21-2. User's Manual IIC_X, V2.0 21-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Note: Per definition, an IIC-Bus system is a Wired-AND configuration. The active (dominant) level is the low level, while the high level is not actively driven by the stations (or nodes), but held through external pull-up devices. For this purpose, the respective pin drivers must be switched to open drain mode. SDA0 SCL0 IIC-Bus A On-Chip IIC-Bus Module IIC Bus Node #x IIC Bus Node #y SDA1 SCL1 IIC-Bus B MCA05464 Figure 21-2 IIC-Bus Configuration Example In an IIC-Bus system, a station may be able to play different roles: Master-Transmitter (a master device which is sending data to one or more slaves), Master-Receiver (a master which is receiving data from a slave), Slave-Transmitter (a slave which is sending data to a master) and Slave-Receiver. User's Manual IIC_X, V2.0 21-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module From the programmer's point of view, the term `IIC-Bus Module' refers to a set of registers which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and including their direction control bits. Figure 21-3 shows the Special Function registers (SFRs) associated with the IIC-Bus Module. Data Registers RTBL RTBH ADR Control/Status Reg. CON CFG ST Interrupt Registers DIC PEIC System Registers P9 DP9 ODP9 ALTSEL0P9 ALTSEL1P9 SYSCON3 OPSEN RTBL / RTBH CON CFG ADR DIC PEIC P9 DP9 ODP9 ALTSELxP9 SCU_SYSCON3 SCU_OPSEN Receive / Transmit Buffer Register Control Register Configuration Register Address Register Data Interrupt Control Register Protocol Event Interrupt Control Register Port P9 Data Register Port P9 Direction Control Register Port P9 Open-Drain Control Register Port P9 Alternate Output Select Register (x = 0, 1) SCU System Control Register 3 SCU OCDS Peripheral Suspend Enable Register MCA05465 Figure 21-3 SFRs Associated with the IIC-Bus Module User's Manual IIC_X, V2.0 21-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.2 Register Description In the following, the registers of the IIC-Bus Module are described in detail. IIC_CON Control Register 15 14 13 12 11 CI rw 10 XSFR (E602H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 STP IGE TRX INT rwh rw rwh rw ACK BUM DIS rwh rwh MOD rw RSC M10 rwh rw Field CI Bits Type Description Transmit Buffer Length Control 00 1 byte (RTB0) 01 2 bytes (RTB1 ... RTB0) 10 3 bytes (RTB2 ... RTB0) 11 4 bytes (RTB3 ... RTB0) Master Stop Control 0 No action 1 Setting bit STP generates a stop condition after the next transmission. Bit BUM is cleared. Note: STP is automatically cleared by a stop condition. [11:10] rw STP 9 rwh IGE 8 rw Ignore End-of-Transmission (IRQE) Interrupt 0 The IIC is stopped at IRQE interrupt 1 The IIC ignores the IRQE interrupt Transmit Select 0 No data is transmitted to the IIC bus 1 Data is transmitted to the IIC bus Note: TRX is set automatically when writing to the transmit buffer. TRX is automatically cleared after the last byte as a slave transmitter. TRX 7 rwh INT 6 rw Interrupt Flag Clear Control 0 Interrupt flag IRQD is cleared by a read/write access to RTB0 ... 3 1 Interrupt flag IRQD is not cleared by a read/write access to RTB0 ... 3 User's Manual IIC_X, V2.0 21-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Field ACKDIS Bits 5 Type rwh Description Acknowledge Pulse Disable 0 An acknowledge pulse is generated for each received byte 1 No acknowledge pulse is generated Note: ACKDIS is automatically cleared by a stop condition. BUM 4 rwh Busy Master 0 Clearing bit BUM immediately generates a stop condition 1 Setting bit BUM generates a start condition in (multi-) Master mode Note: Setting bit BUM while the bus is busy (BB = 1) generates an arbitration lost situation. In this case, BUM is cleared and bit AL is set. BUM cannot be set in slave mode. MOD [3:2] rw Basic Operating Mode 00 IIC module is disabled and initialized (InitMode). Transmissions in progress will be aborted. 01 Slave mode 10 Single-Master mode 11 Multi-Master mode Repeated Start Condition Trigger 0 No operation 1 Generate a repeated start condition in (multi-) master mode. RSC cannot be set in slave mode. Note: RSC is cleared automatically after repeated start condition has been sent. M10 0 rw Slave Address Width Selection 0 7-bit slave address, using ICA[7:1] 1 10-bit slave address, using ICA[9:0] the RSC 1 rwh User's Manual IIC_X, V2.0 21-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_ST Status Register 15 14 13 12 11 10 XSFR (E604H/--) 9 CO rh 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 IRQ IRQ IRQ E P D rwh rwh rwh BB LRB SLA rh rh rh AL ADR rwh rh Field CO Bits [10:8] Type rh Description Transmit Byte Counter Displays the number of correctly transferred bytes. See Section 21.3.4 for details. 000 0 bytes 001 1 byte 010 2 bytes 011 3 bytes 100 4 bytes 1xx Reserved End-of-Data-Transmission Interrupt Req. Flag 0 No interrupt request pending 1 An End-Of-Data-Transmission interrupt request is pending See Section 21.4 for details. Protocol Event Interrupt Request Flag 0 No interrupt request pending 1 A Protocol Event interrupt request is pending See Section 21.4 for details. Data Transfer Event Interrupt Request Flag 0 No interrupt request pending 1 A Data Transfer Event interrupt request is pending See Section 21.4 for details. Bus Busy Flag 0 The IIC-Bus is idle 1 The IIC-Bus is busy Note: Bit BB is always 0 while the IIC module is disabled. IRQE 7 rwh IRQP 6 rwh IRQD 5 rwh BB 4 rh User's Manual IIC_X, V2.0 21-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Field LRB Bits 3 Type rh Description Last Received Bit Bit LRB represents the last bit (i.e. the acknowledge bit) of the last transferred byte. It is automatically cleared by a read/write access to the buffer RTB0 ... 3. Note: If LRB is high (no acknowledge) in slave mode, bit TRX is set automatically to select slave transmit mode. SLA 2 rh Slave Select Flag 0 The IIC-Bus Module is not addressed in Slave mode, or the module is in Master mode. 1 The IIC-Bus Module has been addressed as a slave (own slave address or general address, 00H, was received). Arbitration Lost Flag Bit AL is set when the IIC-Bus Module has tried to become master on the bus but has lost arbitration. Operation is continued until the 9th clock pulse. If multi-master mode is selected, the IIC module temporarily switches to Slave mode after a lost arbitration. Bit IRQP is set along with bit AL. AL must be cleared via software. Address Phase Flag Bit ADR is set after a start condition in Slave mode until the complete address has been received (1 byte in 7-bit address mode, 2 bytes in 10-bit address mode). AL 1 rwh ADR 0 rh User's Manual IIC_X, V2.0 21-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_ADR Address Control Register 15 BRP MOD rw 14 13 12 11 10 rw rw XSFR (E606H/--) 9 8 7 6 5 ICA rw 4 Reset Value: 0000H 3 2 1 0 PREDIV rw rw Field BRPMOD Bits 15 Type rw Description Baudrate Generator Mode Control 0 Mode 0: Reciprocal Divider 1 Mode 1: Fractional Divider Pre-Divider for Baudrate Generation 00 Pre-divider is disabled 01 Pre-divider factor is 8 10 Pre-divider factor is 64 11 Reserved, do not use Own Slave Address Specifies the slave address of the IIC-Bus module 7-bit address mode (CON.M10 = 0): address stored in ICA[7:1] (ICA[9:8] and ICA[0] are read-only, read as 0) 10-bit address mode (CON.M10 = 1): address stored in ICA[9:0] PREDIV [14:13] rw ICA [9:0] rw User's Manual IIC_X, V2.0 21-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_CFG Configuration Control Register XSFR (E600H/--) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 BRP rw SCL SCL SCL EN2 EN1 EN0 rw rw rw SDA SDA SDA EN2 EN1 EN0 rw rw rw Field BRP Bits [15:8] Type rw Description Baudrate Prescaler Value Determines the baudrate for the IIC-Bus module together with bit ADR.BRPMOD and bitfield ADR.PREDIV Enable Bit for SCLx Clock Line These bits determine to which pins the IIC clock line is connected. 0 SCLx pin is disconnected 1 SCLx pin is connected with IIC clock line Enable Bit for SDAx Data Line These bits determine to which pins the IIC data line is connected. 0 SDAx pin is disconnected 1 SDAx pin is connected with IIC data line SCLENx (x = 2 ... 0) 6, 5, 4 rw SDAENx (x = 2 ... 0) 2, 1, 0 rw User's Manual IIC_X, V2.0 21-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_RTBH Receive/Transmit Buffer High 31 30 29 28 27 26 XSFR (E60AH/--) 25 24 23 22 21 20 Reset Value: 0000H 19 18 17 16 RTB3 rwh RTB2 rwh IIC_RTBL Receive/Transmit Buffer Low 15 14 13 12 11 10 XSFR (E608H/--) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 RTB1 rwh RTB0 rwh Field RTBx (x = 3 ... 0) Bits [31:24], [23:16], [15:8], [7:0] Type rwh Description Receive/Transmit Buffer Bytes The buffers contain the data to be sent or which have been received. The buffer size can be selected via bitfield CI, from 1 up to 4 bytes. The contents of RTB0 are sent/received first. Note: If bit INT is set to zero and all bytes (specified in CI) of RTB0 ... 3 are read/written (dependent on bit TRX), IRQD will be cleared by hardware after completion of this access (this supports PEC operation). User's Manual IIC_X, V2.0 21-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.3 IIC-Bus Module Operation The following sections describe the operation of the IIC-Bus Module in the three different modes. In addition, detailed information on the Receive/Transmit Buffer as well as the Baudrate Generator is provided. 21.3.1 Operation in Single-Master Mode In Single-Master Mode, the IIC-Bus Module of the XC167 is the only master controlling the external IIC-Bus, thus, the master can always assume that the bus is free to use. Under normal conditions, there is no possibility for this master to loose arbitration. Software initializes the IIC-Bus Module according to the master operation. There is no need to specify an own slave address in register ADR, as the master can never be addressed by another station. To start a transfer, the master first writes the address of the slave to be contacted (or the general call address to access all stations) into the receive/transmit buffer. In 7-bit address mode, the address is written to bitfield RTB0, bits [7:1]. In 10-bit address mode, the address is written to bitfields RTB0 and RTB1. Bit 0 of RTB0 is the read/write bit R/W, which informs the slave whether the master wants to read from or write to the slave. Then the master sets bit BUM in register CON. This generates a start condition on the bus, the busy bit BB is set, and the transmission of the buffer contents begins. To start a new transfer or to change the transfer direction, the master can generate a repeated start condition. This eliminates the need to first stop bus transactions, and then start again. The repeated start is performed by setting bit RSC in register CON. The busy bit BB remains set. Bit RSC is cleared automatically after the repeated start condition has been generated. When the master is finished with the current bus transaction, it generates a stop condition on the bus by clearing bit BUM. 21.3.2 Operation in Multimaster Mode In Multi-Master Mode, the XC167 is not the only master on the bus and must share IICBus usage with other masters. This requires bus arbitration, as only one master may control the bus at a given time. Thus, when a master tries to take control of the IIC-Bus, it might be that the bus is already in use or that another master is trying to claim the bus at the same time. To detect such situations, each master monitors the bus activity by comparing the level which it wants to output onto the SDA line with the level it reads from the external SDA line. If it finds the case that it wants to output a high level (inactively driven by the master, but usually held through external pull-up devices), but the actual level on the SDA line is a low level, then it recognizes this case as an `arbitration lost' condition, and it needs to backoff. User's Manual IIC_X, V2.0 21-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module It is not only necessary for the loosing master to release the bus in order to allow the other master to control the bus, but it also needs to receive the message from the other master, as it might be addressed as a slave. When the XC167 wants to use the IIC-Bus, it prepares to start a transfer as in SingleMaster Mode. The next recommended step is to poll bit BB to check whether the bus is busy. If BB = 0, then the start condition can be generated by setting bit BUM. If the bus is still free after that, operation continues as in Single-Master Mode. If the bus is already in use, indicated by BB = 1, the master can not take control of the bus and needs to act as a slave (acting as a slave is automatically done in hardware); bit BUM should not be set in this case. If bit BUM is set although the bus is already in use, the Arbitration Lost flag AL is set. However, if testing bit BB showed that the bus is free, and software sets the BUM bit, but at the same time another master tries to get onto the bus, the bus arbitration needs to take place. This is performed such that the master which first detects a mismatch between its intended output level and the actual level on the SDA line looses the arbitration. The Arbitration Lost flag AL is set in this case, the Transmit Selection bit TRX is cleared to 0 (= reception), and the master automatically switches to slave mode to receive the address information. At the end of the address phase, hardware automatically compares the received address with the own station address stored in register ADR. If the two addresses match or if the general call address (00H) has been received, the Slave Select flag SLA in register ST is set to indicate that the device has been contacted. Operation is then continued as described in Slave Mode. Together with bit AL, the Protocol Event interrupt flag IRQP is set, and the respective interrupt request line is activated. Note that a master which has lost arbitration has written its transmit message to the receive/transmit buffer before it has tried to take control of the IIC-Bus. However, after it has lost arbitration, it has switched to Slave Mode, and was therefore receiving the message sent over the bus. This message is then stored in the receive/transmit buffer, overwriting the previous transmit message. Due to the fact that a master must also act as a slave in a multi-master system, the actual implicit default operating mode in Multi-Master Mode is Slave Mode. 21.3.3 Operation in Slave Mode When the XC167 is intended to purely operate as a slave on the IIC-Bus, Slave Mode needs to be selected via bitfield MOD in register CON. The IIC-Bus Module is selected by another master when it receives either its own device address or the general call address during the address phase of a transmission (the byte(s) following a start or repeated start condition). If this is the case, bit SLA in register ST is set, the Protocol Event interrupt flag IRQP is set, and the respective interrupt request line is activated. User's Manual IIC_X, V2.0 21-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module If the device has not been selected, it remains idle in Slave Mode. If the device has been selected, the read/write bit R/W, which has been received together with the address information, needs to be checked by software to determine the further actions. If this bit is 0, the slave remains in receive mode, and can read the incoming message from the buffer RTB0 ... 3. If bit R/W = 1, the master wants to read from the slave device. For this, the slave needs to prepare the data to be transferred to the master. The data is written to the buffer RTB0 ... 3. Writing to the buffer automatically sets the transfer mode bit TRX to one (= transmission). In both cases, operation can only continue when all interrupt flags, IRQD, IRQE, and IRQP, are cleared. Otherwise, the device holds the SCL clock line low to prevent further transactions on the IIC-Bus. In this way, a slave is able to suspend bus activities until it is ready to proceed. When a stop condition or a repeated start condition is detected, bit SLA is cleared (it will be set again if the slave is contacted again at the end of the address phase of the new transaction). 21.3.4 Transmit/Receive Buffer The IIC-Bus Module has a transmit/receive buffer which can be set to a depth of one to four bytes. Access to this buffer is performed via the two registers RTBL and RTBH, each of these represents two bytes of the buffer. The depth of the buffer is specified via bitfield CI in register CON (1, 2, 3 or 4 bytes). For a transmission, the bytes to be transferred are written to the respective buffer bytes, and then transmission is initiated. The data interrupt IRQD is activated when all bytes of the specified buffer have been transmitted. In receive mode, the data interrupt IRQD is activated when all bytes of the specified buffer have been filled with incoming data. A byte counter, CO in the status register ST, counts the bytes which have been transferred from the buffer to the IIC-Bus or vice versa. The contents of this counter is especially of interest in Slave-Transmitter Mode, if the bus transactions have been terminated by an external master before all bytes of the buffer have been transmitted. Software can determine the number of correctly transmitted bytes by reading bitfield CO. In receive mode, bitfield CO needs to be read in case the transactions have been terminated (which activates the Protocol Event interrupt request, IRQP), as it represents the number of correctly received bytes. Bitfield CO is always cleared to 0 by the correct number (defined by bitfield CI) of read/write accesses to the buffer registers. User's Manual IIC_X, V2.0 21-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.3.5 Baud Rate Generation In order to give the user high flexibility in selection of CPU frequency and IIC-Bus baudrate without constraints to baudrate accuracy, a flexible baudrate generator has been implemented. It uses two different modes and an additional pre-divider. Low baudrates may be configured at high precision in mode 0, which is compatible with previous implementations of the IIC-Bus module. High baudrates may be configured precisely in mode 1. Prescale Value BRP fIIC 8:1 64:1 MUX Baudrate Generator Circuitry BRPMOD PREDIV BIIC MCA05466 Figure 21-4 IIC-Bus Module Baudrate Generator Reciprocal Divider Mode (BRPMOD = 0) The resulting baudrate is: IIC B0 IIC = ----------------------------------------------------------------------------- f IIC BRP = ---------------------------------------------------------- - 1 f (21.1) Table 21-1 BRPMOD = 0 IIC-Bus Baudrate Examples for Mode 0 BRP @ 100 kbit/s PREDIV = 00B 63H 3BH 31H 27H 18H 13H PREDIV = 01B 0BH 06H 05H 04H 02H 01H 18H 0EH 0BH 09H 05H 04H BRP @ 400 kbit/s PREDIV = 00B PREDIV = 01B 02H - - - - - fIIC [MHz] 40 24 20 16 10 8 User's Manual IIC_X, V2.0 21-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Fractional Divider Mode (BRPMOD = 1) The resulting baudrate is: B1 IIC = ----------------------------------------------- f IIC x x B1 IIC 1024 x 2 BRP = -------------------------------------------------------------------- f IIC (21.2) IIC-Bus Baudrate Examples for Mode 1 BRP @ 100 kbit/s PREDIV = 00B 03H 04H 05H 06H 0AH 0DH PREDIV = 01B 14H 22H 28H 33H 51H 66H 0AH 11H 14H 1AH 29H 33H BRP @ 400 kbit/s PREDIV = 00B PREDIV = 01B 51H 88H A4H CDH - - fIIC [MHz] 40 24 20 16 10 8 21.3.6 Notes for Programming the IIC-Bus Module It is strictly recommended not to write to the IIC-Bus Module registers while the module is busy with transfers, except when interrupt requests have been generated. In Master Mode (and if operating as active master in Multi-Master Mode), the module is busy as long as the BUM bit is set. In Slave Mode (and if operating as a slave in MultiMaster Mode), the module is busy from a start condition (or repeated start condition) until a stop condition is detected. This is indicated by the busy bit BB. Access to the module's registers should only be performed after appropriate interrupt requests are generated by the module, indicating a pause in or the termination of ongoing transfers. During initialization mode (MOD = 00), all registers can be accessed freely. A change of the transfer direction is only allowed after a protocol interrupt. When operating as a master, software can examine the level of the acknowledge bit returned by the slave via bit LRB (Last Received Bit) in the status register ST. Note that this bit represents the acknowledge bit of the last byte which was transferred before an interrupt request was generated. User's Manual IIC_X, V2.0 21-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.4 Interrupt Request Operation The IIC-Bus Module can generate three different interrupt requests, each with its own request flag. However, due to the nature of these requests, it is sufficient to use only two interrupt nodes to process the requests. As the data interrupt request IRQD and the endof-data-transmission interrupt request IRQE both deal with the end of a transfer of a block of data, their are combined onto one interrupt request line and node, IIC_DIRQ, as shown in Figure 21-5. IRQD Interrupt Request Circuitry IRQE IRQP _ >1 IIC_DIRQ IIC_PEIRQ MCA05467 Figure 21-5 IIC-Bus Module Interrupt Wiring The request flags for the three possible interrupt sources are located in the status register ST. The conditions for the activation of the requests and for handling of the request flags are detailed below. As long as one or more of the interrupt request flags are set, and the IIC-Bus Module operates in Master Mode or has been selected as a slave, the clock line SCL is held at low level to prevent further transactions on the bus. The clock line is released again when all three flags are set to 0. Then, further transactions can take place on the IIC bus. This operation can also be used to control IIC-Bus transactions by setting or clearing the request flags by software. Data Transfer Event Interrupt, IRQD This request is activated and the flag is set when the specified buffer is either empty (in transmit mode) or full (in receive mode). For example, when the buffer size is set to 3 bytes (via CI) and all three buffer locations, RTB0, RTB1, and RTB2, have been written with transmit values, then the request will be activated when the last byte in RTB2 has been sent via the IIC-Bus. IRQD is also activated in Slave-Transmitter Mode, when a transfer was terminated by the current master before all data in the slave's transmit buffer has been sent. This is in addition to the activation of interrupt request IRQE. If the automatic interrupt flag clear operation is selected (bit CON.INT = 0), then flag IRQD is automatically cleared by hardware upon a complete read or write access to the buffer(s) RTB0 ... 3. If CON.INT = 1, then flag IRQD must be cleared by software. User's Manual IIC_X, V2.0 21-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module End-of-Data-Transmission Interrupt, IRQE This request is activated and the flag is set when the current data transfer is terminated either by a repeated start, by a stop, or by a missing acknowledge. In the case of Slave-Transmitter Mode, additionally the Data Transfer interrupt request IRQD will be activated. Flag IRQE must be cleared by software. Protocol Event Interrupt, IRQP This request is activated and the flag is set in Multi-Master mode when the module has lost arbitration. Additionally, the arbitration lost flag AL is set. In Multi-Master and in Slave Mode, this request is activated when either the general call address or the device's own address has been received. Flag IRQP must be cleared by software. Interrupt Nodes The three interrupt request lines are connected to two interrupt nodes (see Figure 21-5): IIC_DIC IIC Data Interrupt Ctrl. Reg. 15 14 13 12 11 10 ESFR (F186H/C3H) 9 8 GPX rw 7 6 5 4 Reset Value: - - 00H 3 2 1 0 ICD ADC IR IE rwh rw ILVL rw GLVL rw IIC_PEIC IIC Protocol Intr. Ctrl. Reg. 15 14 13 12 11 10 ESFR (F18EH/C7H) 9 8 GPX rw 7 6 5 4 Reset Value: - - 00H 3 2 1 0 ICP ADE IR IE rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual IIC_X, V2.0 21-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.5 Port Connection and Configuration The IIC-Bus Module can provide up to three SCL/SDA signal pairs, which can be connected to different pins of the XC167. The individual enable control bits for these options are located in the configuration register CFG. Figure 21-6 illustrates this feature. Port Logic Port Logic Port Logic Enable Port Logic Port Logic Port Logic SDA0 SDA1 SDA2 IIC Bus Module SCL0 SCL1 SCL2 MCA05468 Figure 21-6 IIC-Bus Module Port Pin Connection Options Pin Configuration Due to the Wired-AND configuration of an IIC-Bus system, the port drivers for the SCL and SDA signal lines need to be operating in open-drain mode (no upper transistor). The high level on these lines are held via external pull-up devices (approx. 10 k for operation at 100 kbit/s, 2 k for operation at 400 kbit/s). All pins of the XC167 that are to be used for IIC-Bus communication provide open-drain drivers, and must be programmed to output operation, and their alternate function must be enabled (by setting the respective port output latch to 1), before any communication can be established. The input lines from the SCL/SDA pins are always connected to the IIC-Bus Module, and do not require special programming. The inputs feature digital input filters in order to improve the rejection of noise from the external bus lines. User's Manual IIC_X, V2.0 21-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Table 21-3 shows the required register setting to configure the IO lines of the IIC-Bus Module for master and slave mode operation. Please note that all lines must be configured for open-drain output operation. This is required, e.g., to enable a slave module to actively hold the SCL line low as long as it cannot accept further bus transactions. The IIC-Bus Module deactivates output lines by setting the line to high level, which results in a passive level at the open-drain output. Table 21-3 Port Lines Bus A: P9.0 / SDA0 P9.1 / SCL0 Bus B: P9.2 / SDA1 P9.3 / SCL1 Bus C: P9.4 / SDA2 P9.5 / SCL2 ALTSEL0P9.P4 = 1 and ALTSEL1P9.P4 = X ALTSEL0P9.P5 = 1 and ALTSEL1P9.P5 = X DP9.P4 = 1 DP9.P5 = 1 ODP9.P4 = 1 ODP9.P5 = 1 ALTSEL0P9.P2 = 1 and ALTSEL1P9.P2 = 0 ALTSEL0P9.P3 = 1 and ALTSEL1P9.P3 = 0 DP9.P2 = 1 DP9.P3 = 1 ODP9.P2 = 1 ODP9.P3 = 1 ALTSEL0P9.P0 = 1 and ALTSEL1P9.P0 = X ALTSEL0P9.P1 = 1 and ALTSEL1P9.P1 = 0 DP9.P0 = 1 DP9.P1 = 1 ODP9.P0 = 1 ODP9.P1 = 1 IIC IO Selection and Setup Alternate Select Register Direction Control Register Open Drain Control Register User's Manual IIC_X, V2.0 21-20 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.6 Interfaces of the IIC-Bus Module In the XC167, the IIC-Bus Module is connected to IO ports and other internal modules according to Figure 21-7. The input/output lines of the module are connected to pins of Ports P9. The 2 interrupt request lines are connected to the Interrupt Control Block. Please note that two of the thee possible interrupt sources in the IIC-Bus Module or ORed together onto the request line IIC_DIRQ (see Section 21.4). Clock control and emulation control of the IIC-Bus Module is handled by the System Control Unit, SCU. System Control Unit (SCU) fIIC IICDIS IIC-Bus Module SDA_OUT [2:0] SCL_OUT [2:0] Port P9 Control P9.0/SDA0 P9.1/SCL0 P9.2/SDA1 P9.3/SCL1 P9.4/SDA2 P9.5/SCL2 MCA05469 Interrupt Control Block IIC_DIRQ IIC_PEIRQ SDA_IN [2:0] SCL_IN [2:0] Figure 21-7 IIC-Bus Module IO Interface User's Manual IIC_X, V2.0 21-21 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 21.7 IIC-Bus Overview Figure 21-8 gives a brief overview of the major definitions of the IIC-Bus operation. Normal Data Transfer SCL SDA Data Stable Start and Stop Conditions SCL SDA Start Address and Acknowledge SCL SDA Transmitter SDA Receiver Start Clock Synchronization SCL Master A 1st 2nd 8th 9th Stop A6 A5 A4 A0 R/W ACK Bit SCL Master B External SCL Master Arbitration SCL Master A & B SDA A6 A5 Master A A4 Master B lost arbitration A3 A2 MCT05470 Figure 21-8 IIC-Bus Characteristics User's Manual IIC_X, V2.0 21-22 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22 22.1 22.1.1 TwinCAN Module Kernel Description Overview The TwinCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 part B (active). Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share the TwinCAN module's resources in order to optimize the CAN bus traffic handling and to minimize the CPU load. The flexible combination of Full-CAN functionality and FIFO architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. Improved CAN bus monitoring functionality as well as the increased number of message objects permit precise and comfortable CAN bus traffic handling. Depending on the application, each of the 32 message objects can be individually assigned to one of the two CAN nodes. Gateway functionality allows automatic data exchange between two separate CAN bus systems, which reduces CPU load and improves the real time behavior of the entire system. The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connect each CAN node to a bus transceiver. Features * * * * * CAN functionality according to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1 MBaud is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. Full-CAN functionality: 32 message objects can be individually - assigned to one of the two CAN nodes, - configured as transmit or receive object, - participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm, - setup to handle frames with 11-bit or 29-bit identifiers, - provided with programmable acceptance mask register for filtering, - monitored via a frame counter, - configured to Remote Monitoring Mode. Up to eight individually programmable interrupt nodes can be used. CAN Analyzer Mode for bus monitoring is implemented. 22-1 V2.0, 2004-04 * * User's Manual TwinCAN_X1, V2.1 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module TwinCAN Module Kernel Clock Control fCAN CAN Node A CAN Node B TxDCA RxDCA Address Decoder CAN Message Object Buffer Interrupt Control TxDCB RxDCB TwinCAN Control Port Control MCB05471 Figure 22-1 General Block Diagram of the TwinCAN Module The CAN kernel (Figure 22-2) is split into * A global control shell, subdivided into the initialization logic, the global control and status logic and the interrupt request compressor. - The initialization logic sets up all submodules after power-on or reset. After finishing the initialization of the node control logic and its associated message objects, the respective CAN node is synchronized with the connected CAN bus. - The global control and status logic informs the CPU about pending object transmit and receive interrupts and about the recent transfer history. - The interrupt request compressor condenses the interrupt requests from 72 sources, belonging to CAN node A and B, to 8 interrupt nodes. A message buffer unit, containing the message buffers, the FIFO buffer management, the gateway control logic and a message-based interrupt request generation unit. - The message buffer unit stores up to 32 message objects of 8 bytes maximum data length. Each object has an identifier and its own set of control and status bits. After initialization, the message buffer unit can handle reception and transmission of data without CPU supervision. - The FIFO buffer management stores the incoming and outgoing messages in a circular buffer and determines the next message to be processed by the CAN controller. - The gateway control logic transfers a message from CAN node A to CAN node B or vice versa. - The interrupt request generation unit indicates message-specifically the reception or transmission of an object. 22-2 V2.0, 2004-04 * User's Manual TwinCAN_X1, V2.1 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module * Two separate CAN nodes, subdivided into a bit stream processor, a bit timing control unit, an error handling logic, an interrupt request generation unit and a node control logic: - The bit stream processor performs data, remote, error and overload frames according to the ISO-DIS 11898 standard. The serial data flow between the CAN bus line, the input/output shift register and the CRC register is controlled as well as the parallel data flow between the I/O shift register and the message buffer unit. - The bit timing control unit defines the sampling point in respect to propagation time delays and phase shift errors and performs the resynchronization. - The error handling control logic manages the receive and the transmit error counter. According the contents in both timers, the CAN controller is set into an error-active, error-passive or bus-off state. - The interrupt request generation unit signals globally the successful end of a message transmit or receive operation, all kinds of transfer problems like bit stuffing errors, format, acknowledge, CRC or bit state errors, every change of the CAN bus warning level or of the bus-off state. - The node control logic enables and disables the node specific interrupt sources, enters the CAN analyzer mode and administrates a global frame counter. To CAN Bus A To CAN Bus B Bit Stream Processor Node A Bit Timing Control Control Logic Error Handling Interrupt Request Generation Bit Stream Processor Bit Timing Control Node B Control Logic Error Handling Interrupt Request Generation Message Object Buffers Interrupt Request Generation FIFO Control Gateway Control TwinCAN Control Interrupt Request Compressor Global Status and Control Logic Initialization Logic MCB05472 Figure 22-2 Detailed Block Diagram of the TwinCAN Kernel User's Manual TwinCAN_X1, V2.1 22-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.2 TwinCAN Control Shell 22.1.2.1 Initialization Processing After an external hardware reset or while it is bus-off, the respective CAN controller node is logically disconnected from the associated CAN bus and does not participate in any message transfer. This is indicated by the ACR/BCR control register bit INIT = `1', which is automatically set in case of a reset or while the CAN node is bus-off. Furthermore, the CAN node will be disconnected by setting bit INIT to `1' via software. While INIT is active, all message transfers between the affected CAN node controller and its associated CAN bus are stopped and the bus output pin (TXDC) is held on `1' level (recessive state). After an external hardware reset, all control and message object registers are reset to their associated reset values. During the bus-off-state or after a write access to register ACR/BCR with INIT = `1', all respective control and message object registers hold their current values (except the error counters). Resetting bit INIT to `0' without being in the bus-off-state starts the synchronization sequence (= connection to the CAN bus), which has to monitor at least one bus-idle event (11 consecutive `recessive' bits) on the associated CAN bus before the node is allowed to take part in CAN traffic again. During the bus-off recovery sequence: * * The receive and the transmit error counter within the error handling logic are reset. 128 bus-idle events (11 consecutive `recessive' bits) have to be detected, before the synchronization sequence can be initiated. The monitoring of the bus idle events is immediately started by hardware after entering the bus-off state. The number of already detected bus-idle events is counted and indicated by the receive error counter. The reconnect procedure tests bit INIT by hardware after 128 bus-idle events. If INIT is still set, the affected CAN node controller waits until INIT is cleared and at least one bus-idle event is detected on the CAN bus, before the node takes part in CAN traffic again. If INIT has been already cleared, the message transfer between the affected CAN node controller and its associated CAN bus is immediately enabled. * User's Manual TwinCAN_X1, V2.1 22-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.2.2 Interrupt Request Compressor The CAN module is equipped with 32 x 2 message object specific interrupt request sources and 2 x 4 node control interrupt request sources. A request compressor condenses these 72 sources to 8 CAN interrupt nodes reporting the interrupt requests of the CAN module. Each request source is provided with an interrupt node pointer, selecting the interrupt node to start the associated service routine in order to increase flexibility in interrupt processing. Each of the 8 CAN interrupt nodes can trigger an independent interrupt routine with its own interrupt vector and its own priority. Request Compressor CAN Interrupt Node 0 Interrupt Request Source k _ >1 To Interrupt Controller Interrupt Node Pointer of Request Source k CAN Interrupt Node 7 Interrupt Request Source n _ >1 To Interrupt Controller Interrupt Node Pointer of Request Source n MCA05473 Figure 22-3 Interrupt Node Pointer and Interrupt Request Compressor Note: All interrupts are event-oriented. The event sets the corresponding indication flag and can generate an interrupt to the system. An interrupt event occurring while its corresponding indication flag is still set, can generate a new interrupt. User's Manual TwinCAN_X1, V2.1 22-5 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.2.3 Global Control and Status Logic The receive interrupt pending register RXIPND contains 32 individual flags indicating a pending receive interrupt for the associated message objects. Flag RXIPNDn is set by hardware if the corresponding message object has correctly received a data or remote frame and the correlated interrupt request generation has been enabled by RXIEn = `10'. RXIPNDn can be cleared by software by resetting bit INTPNDn in the corresponding message object control register MSGCTRn. The transmit interrupt pending register TXIPND has a similar functionality as the RXIPND register and provides identical information about pending transmit interrupts. User's Manual TwinCAN_X1, V2.1 22-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.3 CAN Node Control Logic 22.1.3.1 Overview Each node is equipped with an individual node control logic configuring the global behavior and providing status information. The configuration mode is activated when the ACR/BCR register bit CCE is set to `1'. This mode allows modifying the CAN bit timing parameters and the error counter registers. The CAN analyzer mode is activated when bit CALM in control register ACR/BCR is set to `1'. In this operation mode, data and remote frames are monitored without an active participation in any CAN transfer (CAN transmit pin is held on recessive level). Incoming remote frames are stored in a corresponding transmit message object, while arriving data frames are saved in a matching receive message object. In CAN analyzer mode, the entire configuration information of the received frame is stored in the corresponding message object and can be evaluated by the CPU concerning their identifier, XTD bit information and data length code. If the remote monitoring mode is active by RMM = `1', this information is also available for received remote frames. Incoming frames are not acknowledged and no error frames are generated. Neither remote frames are answered by the corresponding data frame nor data frames can be transmitted by setting TXRQ, if CAN analyzer mode is enabled. Receive interrupts are generated (if enabled) for all correctly received frames and the respective remote pending RMTPNDn is set in case of received remote frames. The node specific interrupt configuration is also defined by the node control logic via the ACR/BCR register bits SIE, EIE and LECIE: * * * If control bit SIE is set to `1', a status change interrupt occurs when the ASR/BSR register has been updated (by each successfully completed message transfer). If control bit EIE is set to `1', an error interrupt is generated when a bus-off condition has been recognized or the error warning level has been exceeded or underrun. If control bit LECIE is set to `1', a last error code interrupt is generated when an error code is set in bitfield LEC in the status registers ASR or BSR. The status register (ASR/BSR) provides an overview about the current state of the respective TwinCAN node: * * * * Flag TXOK is set when a message has been transmitted successfully and acknowledged by at least one other CAN node, flag RXOK indicates an error-free reception of a CAN bus message, bitfield LEC indicates the last error occurred on the CAN bus. Stuff, form, and CRC errors as well as bus arbitration errors (Bit0, Bit1) are reported, bit EWRN is set when at least one of the error counters in the error handling logic has reached the error warning limit (default value 96), User's Manual TwinCAN_X1, V2.1 22-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module * bit BOFF is set when the transmit error counter exceeded the error limit of 255 and the respective CAN node controller has been logically disconnected from the associated CAN bus. The CAN frame counter can be used to check the transfer sequence of message objects or to obtain information about the time instant, a frame has been transmitted or received from the associated CAN bus. CAN frame counting is performed by a 16-bit counter, which is controlled by register AFCR/BFCR. Bitfield CFCMD defines the operation mode and the trigger event incrementing the frame counter: * * * * After correctly transmitted frames, after correctly received frames, after a foreign frame on the CAN bus (not transmitted/received by the CAN node itself), at beginning of a new bit time. The captured frame counter value is copied to the CFCVAL field of the associated MSGCTRn register at the end of the monitored frame transfer. Flag CFCOV is set on a frame counter overflow condition (FFFFH to 0000H) and an interrupt request is generated if bit CFCIE is set to `1'. User's Manual TwinCAN_X1, V2.1 22-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.3.2 Timing Control Unit According to ISO-DIS 11898 standard, a CAN bit time is subdivided into different segments (Figure 22-4). Each segment consists of multiples of a time quantum tq. The magnitude of tq is adjusted by the bitfield BRP and by bit DIV8X, both controlling the baud rate prescaler (see bit timing register ABTR/BBTR). The baud rate prescaler is driven by the CAN module clock fCAN. 1 Bit Time TSync TProp TSeg1 Tb1 TSeg2 Tb1 Sync. Segment 1 Time Quantum (tq) Sample Point Transmit Point MCT05474 Figure 22-4 CAN Bus Bit Timing Standard The synchronization segment (TSync) allows a phase synchronization between transmitter and receiver time base. The synchronization segment length is always 1 tq. The propagation time segment (TProp) takes into account the physical propagation delay in the transmitter output driver, on the CAN bus line and in the transceiver circuit. For a working collision detect mechanism, TProp has to be two times the sum of all propagation delay quantities rounded up to a multiple of tq. The phase buffer segments 1 and 2 (Tb1, Tb2) before and after the signal sample point are used to compensate a mismatch between transmitter and receiver clock phase detected in the synchronization segment. The maximum number of time quanta allowed for resynchronization is defined by bitfield SJW in bit timing register ABTR/BBTR. The propagation time segment and the phase buffer segment 1 are combined to parameter TSeg1, which is defined by the value TSEG1 in the respective bit timing register ABTR/BBTR. A minimum of 3 time quanta is requested by the ISO standard. Parameter TSeg2, which is defined by the value of TSEG2 in the bit timing register ABTR/BBTR, covers the phase buffer segment 2. A minimum of 2 time quanta is requested by the ISO standard. According ISO standard, a CAN bit time, calculated as the sum of TSync, TSeg1 and TSeg2, must not fall below 8 time quanta. Note: The access to bit timing register ABTR/BBTR is only enabled if bit CCE in control register ACR/BCR is set to `1'. User's Manual TwinCAN_X1, V2.1 22-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Calculation of the Bit Time tq = (BRP + 1) / fCAN, if DIV8X = `0' = (BRP + 1) / 8 x fCAN, if DIV8X = `1' TSync = 1 tq TSeg1 = (TSEG1 + 1) x tq (min. 3 tq) TSeg2 = (TSEG2 + 1) x tq (min. 2 tq) bit time = TSync + TSeg1 + TSeg2 (min. 8 tq) To compensate phase shifts between clocks of different CAN controllers, the CAN controller has to synchronize on any edge from the recessive to the dominant bus level. If the hard synchronization is enabled (at the start of frame), the bit time is restarted at the synchronization segment. Otherwise, the resynchronization jump width TSJW defines the maximum number of time quanta a bit time may be shortened or lengthened by one resynchronization. The value of SJW is programmed in the ABTR/BBTR registers. TSJW = (SJW + 1) x tq TSeg1 TSJW + Tprop TSeg2 TSJW The maximum relative tolerance for fCAN depends on the phase buffer segments and the resynchronization jump width. dfCAN min (Tb1, Tb2) / 2 x (13 x bit time - Tb2) AND dfCAN TSJW / 20 x bit time Calculation of the Baudrate Baudrate = fCAN / ((BRP + 1) x (1 + TSeg1 + TSeg2)) User's Manual TwinCAN_X1, V2.1 22-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.3.3 Bitstream Processor Based on the objects in the message buffer, the bitstream processor generates the remote and data frames to be transmitted via the CAN bus. It controls the CRC generator and adds the checksum information to the new remote or data frame. After including the start of frame bit SOF and the end of frame field EOF, the bitstream processor starts the CAN bus arbitration procedure and continues with the frame transmission when the bus was found in idle state. While the data transmission is running, the bitstream processor monitors continuously the I/O line. If (outside the CAN bus arbitration phase or the acknowledge slot) a mismatch is detected between the voltage level on the I/O line and the logic state of the bit currently sent out by the transmit shift register, a last error interrupt request is generated and the error code is indicated by bitfield LEC in status register ASR/BSR. An incoming frame is verified by checking the associated CRC field. When an error has been detected, the last error interrupt request is generated and the associated error code is presented in status register ASR/BSR. Furthermore, an error frame is generated and transmitted on the CAN bus. After decomposing a faultless frame into identifier and data portion, the received information is transferred to the message buffer executing remote and data frame handling, interrupt generation and status processing. 22.1.3.4 Error Handling Logic The error handling logic is responsible for the fault confinement of the CAN device. Its two counters, the receive error counter and the transmit error counter (control registers AECNT, BECNT), are incremented and decremented by commands from the bit stream processor. If the bit stream processor itself detects an error while a transmit operation is running, the transmit error counter is incremented by 8. An increment of 1 is used, when the error condition was reported by an external CAN node via an error frame generation. For error analysis, the transfer direction of the disturbed message and the node, recognizing the transfer error, are indicated in the control registers AECNT, BECNT. According to the values of the error counters, the CAN controller is set into the states error-active, error-passive or bus-off. The CAN controller is in error-active state, if both error counters are below the errorpassive limit of 128. It is in error-passive state, if at least one of the error counters equals or exceeds 128. The bus-off state is activated if the transmit error counter equals or exceeds the bus-off limit of 256. This state is reported by flag BOFF in the ASR/BSR status register. The device remains in this state, until the bus-off recovery sequence is finished. Additionally, there is the bit EWRN in the ASR/BSR status register, which is set if at least one of the error counters equals or exceeds the error warning limit defined by bitfield EWRNLVL in the control registers AECNT, BECNT. Bit EWRN is reset if both error counters fall below the error warning limit again. User's Manual TwinCAN_X1, V2.1 22-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.3.5 Node Interrupt Processing Each CAN node is equipped with 4 interrupt sources supporting the * * * global transmit/receive logic, CAN frame counter, error reporting system. SIE TXOK Global CAN Transmit and Receive Logic RXOK LEC _ >1 LECIE TRINP LECINP EWRN BOFF _ >1 EINP EIE CAN Frame Counter CFCINP CFCOV CFCIE MCA05475 Figure 22-5 Node Specific Interrupt Control If enabled by bit SIE = `1' in the ACR/BCR register, the global transmit/receive logic generates an interrupt request, if the node status register (ASR/BSR) is updated after finishing a faultless transmission or reception of a message object. The associated interrupt node pointer is defined by bitfield TRINP in control register AGINP/BGINP. An error is reported by a last error code interrupt request, if activated by LECIE = `1' in the ACR/BCR register. The corresponding interrupt node pointer is defined by bitfield LECINP in control register AGINP/BGINP. The CAN frame counter creates an interrupt request upon an overflow, when the AFCR/BFCR control register bit CFCIE is set to `1'. Bitfield CFCINP, located also in the AGINP/BGINP control register, selects the corresponding interrupt node pointer. The error logic monitors the number of CAN bus errors and sets or resets the error warning bit EWRN according to the value in the error counters. If bit EIE in control User's Manual TwinCAN_X1, V2.1 22-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module register ACR/BCR is set to `1', an interrupt request is generated on any modification of bits EWRN and BOFF. The associated interrupt node pointer is defined by bitfield EINP in control register AGINP/BGINP. 22.1.3.6 Message Interrupt Processing Each message object is equipped with 2 interrupt request sources indicating the successful end of a message transmission or reception. Correct Transfer of Message Object n Transmit TXINP TXIE TXIPND _ >1 INTPND Receive RXINP RXIE RXIPND MCA05476 Figure 22-6 Message Specific Interrupt Control The message based transfer interrupt sources are enabled, if bit TXIE or RXIE in the associated message control register MSGCTRn are set to `10'. The associated interrupt node pointers are defined by bitfields RXINP and TXINP in message configuration register MSGCFGn. 22.1.3.7 Interrupt Indication The AIR/BIR register provides an INTID bitfield indicating the source of the pending interrupt request with the highest internal priority (lowest message object number). The type of the monitored interrupt requests, taken into account by bitfield INTID, can be selected by registers AIMR0/AIMR4 and BIMR0/BIMR4 containing a mask bit for each interrupt source. If no interrupt request is pending, all bits of AIR/BIR are cleared. The interrupt requests INTPNDn have to be cleared by software. User's Manual TwinCAN_X1, V2.1 22-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Interrupt Request Source IMR4 Mask Register IMC34 IMC33 IMC32 INTID Value TXOK Global CAN Transmit and Receive Logic RXOK LEC _ >1 _ >1 INTD = 1 _ >1 EWRN BOFF MCA05477 Figure 22-7 INTID Mask for Global Interrupt Request Sources Registers AIMR0/4 and BIMR0/4 contain a mask bit for each interrupt source (AIMR0/BIMR0 for message specific interrupt sources and AIMR4/BIMR4 for the node specific interrupt sources). If a mask bit is reset, the corresponding interrupt source is not taken into account for the generation of the INTID value. AIMR0 Mask Register IMCn Message Control Register for Object n INTPNDn INTID = n + 2 BIR Interrupt Pending Register AIR Interrupt Pending Register INTID = n + 2 IMCn BIMR0 Mask Register MCA05478 Figure 22-8 INTID Mask for Message Interrupt Request Sources User's Manual TwinCAN_X1, V2.1 22-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.4 Message Handling Unit A message object is the basic information unit exchanged between the CPU and the CAN controller. 32 message objects are provided by the internal CAN memory. Each of these objects has an identifier, its own set of control and status bits and a separate data area. Each message object covers 32 bytes of internal memory subdivided into control registers and data storage as illustrated in Figure 22-9. Module Offset + 300H + n*20H Message Object n Data Arbitration (Identifier) Acceptance Mask Message Control Message Configuration FIFO/Gateway Control +00H +08H +0CH +10H +14H +18H MCA05479 Figure 22-9 Structure of a Message Object In normal operation mode, each message object is associated with one CAN node. Only in shared gateway mode, a message object can be accessed by both CAN nodes (according to the corresponding bitfield NODE). In order to be taken into account by the respective CAN node control logic, the message object must be declared valid in its associated message control register (bit MSGVAL). When a message object is initialized by the CPU, bitfield MSGVAL in message control register MSGCTRn should be reset, inhibiting a read or write access of the CAN node controller to the associated register and data buffer storage. Afterwards, the message identifier and operation mode (transmit, receive) must be defined. If a successful transmission and/or reception of a message object should be followed by the execution of an interrupt service routine, the respective bitfields TXIE and RXIE have to be set and the interrupt pending indicator (bitfield INTPND) should be reset. If the automatic response of an incoming remote frame with matching identifier is not requested, the respective transmission message object should be configured with CPUUPD = `10'. As soon as bitfield MSGVAL is set to `10', the respective message object is operable and taken into account by the associated CAN node controller. User's Manual TwinCAN_X1, V2.1 22-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.4.1 Arbitration and Acceptance Mask Register The arbitration register MSGARn is used to filter the incoming messages and to provide the outgoing messages with an identifier. The acceptance mask register MSGAMRn may be used to disable some identifier bits of an incoming message for the acceptance test. The identifier of a received message is compared (bitwise XOR) to the identifiers of all message objects stored in the internal CAN controller memory. The compare operation starts at object 0 and takes into account all objects with * * * * * a valid message flag (MSGVAL = `10'), a suitable NODE declaration (register MSGCFGn), a cleared DIR control bit (receive message object) for data frame reception, DIR = `1' (transmit message object) for remote frame reception, a matching identifier length declaration (XTD = `1' marks extended 29-bit identifiers, XTD = `0' indicates standard 11 bit identifiers). The result of the compare operation is bit-by-bit ANDED with the contents of the acceptance mask register (Figure 22-10). If concordance is detected, the received message is stored into the CAN controller's message object. The compare operation is finished after analyzing message object 31. Note: Depending on the allocated identifiers and the corresponding mask register contents, multiple message objects may fulfill the selection criteria described above. In this case, the received frame is stored in the fitting message object with the lowest message number. Identifier of Received Frame Bitwise XOR =1 Identifier of Message Object n `0' = Bit Match `1' = No Match Acceptance Mask of Message Object n & Bitwise AND Result = 0: ID of the received frame fits to message object n Result > 0: ID of the received frame does not fit to message object n MCA05480 Figure 22-10 Acceptance Filtering for Received Message Identifiers User's Manual TwinCAN_X1, V2.1 22-16 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.4.2 Handling of Remote and Data Frames Message objects can be set up for transmit or receive operation according to the selected value for control bit DIR. The impact of the message object type on the associated CAN node controller concerning the generation or reception of remote and data frames is illustrated in Table 22-1. Table 22-1 Handling of Remote and Data Frames A transmission request (TXRQ = `10') for this message object generates ... Receive Object (receives data frames, transmits remote frames, control bit DIR = `0') Transmit Object (transmits data frames, receives remote frames, control bit DIR = `1') If a data frame with If a remote frame matching identifier with matching identifier is is received ... received ... ... a remote frame. ... the data frame is ... the remote frame is NOT taken into The requested data stored in this account. message object. frame is stored in this message object on reception. ... the data frame is ... a data frame NOT stored. based upon the information stored in this message object. ... the remote frame is stored in this message object and RMTPND and TXRQ are set to `10'. A data frame, based upon the information stored in this message object, is automatically generated if CPUUPD is set to `01'. User's Manual TwinCAN_X1, V2.1 22-17 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.4.3 Handling of Transmit Message Objects A message object with direction flag DIR = `1' (message configuration register MSGCFGn) is handled as transmit object. All message objects with bitfield MSGVAL = `10' are operable and taken into account by the CAN node controller operation described below. During the initialization phase, the transmit request bitfield (TXRQ), the new information bitfield (NEWDAT) should be reset to `01' and the update in progress by CPU bitfield (CPUUPD) in register MSGCTRn should be reset to `10'. The message bytes to be transmitted are written into the data partition of the message object (MSGDRn0, MSGDRn4). The number of message bytes to be transmitted has to be written to bitfield DLC in register MSGCFGn. The selected identifier has to be written to register MSGARn. Then, bitfield NEWDAT in register MSGCTRn should be set to `10' and bitfield CPUUPD should be reset to `01' by the CPU. When the remote monitoring mode is enabled (RMM = `1' in MSGCFGn), the identifier and the data length code of a received remote frame will be copied to the corresponding transmit message object, if a matching identifier was found during the compare and mask operation with all CAN message objects. The copy procedure may change the identifier in the transmit message object, if some MSGAMRn mask register bits have been set to `0'. As long as bitfield MSGVAL in register MSGCTRn is set to `10', the reception of a remote frame with matching identifier automatically sets bitfield TXRQ to `10'. Simultaneously, bitfield RMTPND in register MSGCTRn is set to `10' in order to indicate the reception of an accepted remote frame. Alternatively, TXRQ may be set by the CPU via a write access to register MSGCTRn. If the transmit request bitfield TXRQ is found at `10' (while MSGVAL = `10' and CPUUPD = `01') by the appropriate CAN controller node, a data frame based upon the information stored in the respective transmit message object is generated and automatically transferred when the associated CAN bus is idle. If bitfield CPUUPD in register MSGCTRn is set to `10', the automatic transmission of a message object is prohibited and flag TXRQ is not evaluated by the respective CAN node controller. The CPU can release the pending transmission by clearing CPUUPD. This allows the user to listen on the bus and to answer remote frames under software control. When the data partition of a transmit message object has to be updated by the CPU, bitfield CPUUPD in message control register MSGCTRn should be set to `10', inhibiting a read or write access of the associated CAN node controller. If a remote frame with an accepted identifier arrives during the update of a message object's data storage, bitfields TXRQ and RMTPND are automatically set to `10' and the transmission of the corresponding data frame is pending until CPUUPD is reset again. User's Manual TwinCAN_X1, V2.1 22-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module If several valid message objects with pending transmission request are noticed by the associated CAN node controller, the contents of the message object with the lowest message number is transmitted first. Bitfield NEWDAT is internally reset by the respective CAN node controller when the contents of the selected message object's data registers is copied to the bitstream processor. Bitfields RMTPND and TXRQ are automatically reset when the message object has been successfully transmitted. The captured value of the frame counter is copied to bitfield CFCVAL in register MSGCTRn and a transmit interrupt request is generated (INTPNDn and TXIPNDn are set) if enabled by TXIE = `10'. Then the Frame Counter is incremented by one if enabled in control register AFCR/BFCR. When a data frame with matching identifier is received, it is ignored by the respective transmit object and not indicated by any interrupt request. User's Manual TwinCAN_X1, V2.1 22-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module yes Bus Free ? no no TXRQ = `10' CPUUPD = `01' yes NEWDAT := `01' Copy Message to Bitstream Processor Matching Remote Frame Received ? yes TXRQ := `10' RMTPND := `10' no Send Message RXIE := `10' no no Transmission Successful ? yes yes INTPND := `10' NEWDAT = `10' no TXRQ := `01' RMTPND := `01' yes no TXIE = `10' yes INTPND := `10' `01' : Reset `10' : Set MCA05481 Figure 22-11 Handling of Message Objects with Direction = `1' = Transmit by the CAN Controller Node Hardware User's Manual TwinCAN_X1, V2.1 22-20 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.4.4 Handling of Receive Message Objects A message object with direction flag DIR = `0' (message configuration register MSGCFGn) is handled as receive object. In the initialization phase, the transmit request bitfield (TXRQ), the message lost bitfield (MSGLST) and the NEWDAT bitfield in register MSGCTR should be reset. All message objects with bitfield MSGVAL = `10' are operable and taken into account by the CAN node controller operation described below. When a data frame has been received, the new information is stored in the data partition of the message object (MSGDRn0, MSGDRn4) and the bitfield DLC in register MSGCFG is updated with the number of received bytes. Unused message bytes will be overwritten by non-specified values. If the NEWDAT bitfield in register MSGCTR is still set, the CAN controller assumes an overwrite of the previously stored message and signals a data loss by setting bitfield MSGLST. In any case, bitfield NEWDAT is automatically set to `10' reporting an update of the data register by the CAN controller. The captured value of the frame counter is copied to bitfield CFCVAL in register MSGCTRn and a receive interrupt request is generated (INTPNDn and RXIPNDn are set) if enabled by RXIE = `10'. Then the frame counter is incremented by one if enabled in control register AFCR/BFCR. When a receive object is marked to be transmitted (TXRQ = `10'), bit MSGLST changes automatically to CPUUPD. If CPUUPD is reset to `01', the CAN controller generates a remote frame which is emitted to the other communication partners via CAN bus. In case of CPUUPD = `10', the remote frame transfer is prohibited until the CPU releases the pending transmission by resetting CPUUPD to `01'. RMTPND and TXRQ are automatically reset, when the remote frame has been successfully transmitted. Finally, a transmit interrupt request is generated if enabled by TXIE = `10'. When a remote frame with matching identifier is received, it is not answered and not indicated by an interrupt request. User's Manual TwinCAN_X1, V2.1 22-21 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module yes Bus Idle ? no no TXRQ = `10' CPUUPD = `01' yes NEWDAT := `01' yes Load Identifier and Control Bits into Bitstream Processor Matching Data Frame Received ? yes no NEWDAT = `10' no Send Remote Frame MSGLST := `10' no Transmission Successful ? yes TXRQ := `01' RMTPND := `01' Store Message NEWDAT := `10' TXRQ := `01' RMTPND := `01' no TXIE = `10' RXIE := `10' no yes INTPND := `10' `01' : Reset `10' : Set yes INTPND := `10' MCA05482 Figure 22-12 Handling of Message Objects with Direction = `0' = Receive by the CAN Controller Node Hardware User's Manual TwinCAN_X1, V2.1 22-22 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.4.5 Single Data Transfer Mode The single data transfer mode is a useful feature in order to broadcast data over the CAN bus without unintended doubling of information. The single data transfer mode is selected via bit SDT in the FIFO/Gateway control register MSGFGCRn. Each received data frame with matching identifier is automatically stored in the corresponding receive message object if MSGVAL is set to `10'. When data frames addressing the same message object are received within a short time interval, information might get lost (indicated by MSGLST = `10'), if the CPU has not processed the former message object contents in time. Each arriving remote frame with matching identifier is answered by a data frame based on the contents of the corresponding message object. This behavior may lead to multiple generation and transmission of identical data frames according to the number of accepted remote requests. If SDT is set to `1', the CAN node controller automatically resets bit MSGVAL in a message object after receiving a data frame with corresponding identifier. All following data frames, addressing the disabled message object, are ignored until MSGVAL is set again by the CPU. If SDT is set to `1', the CAN node controller automatically resets bit MSGVAL in the addressed message object, when the transmission of the corresponding data frame has been finished successfully. In consequence, all following remote requests concerning the disabled message object are ignored until MSGVAL is set again by the CPU. This feature allows for transmitting data in a consecutive manner without unintended doubling of any information. If SDT is cleared, control bitfield MSGVAL is not reset by the CAN node controller. User's Manual TwinCAN_X1, V2.1 22-23 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.5 CAN Message Object Buffer (FIFO) In case of a high CPU load, it may be difficult to process an incoming data frame before the corresponding message object is overwritten with the next input data stream provided by the CAN node controller. Depending on the application, it could be also necessary to ensure a minimum data frame generation rate to fulfill external real time requirements. Therefore, a message buffer facility has been implemented in order to avoid a loss of incoming messages and to minimize the setup time for outgoing messages. Some message objects can be configured as a base object using succeeding slave message objects as individual buffer storage (building a circular buffer used as message FIFO). FIFO Object n + 7 FIFO Object n + 6 FIFO Object n + 5 To / From CAN Bus Protocol Layer FIFO Object n + 4 FIFO Object n + 3 FIFO Object n + 2 FIFO Object n + 1 Message Transferred Select Object FIFO Control Unit MCA05483 FIFO Object n (base) Control Status Figure 22-13 FIFO Buffer Control Structure The number of base and slave message objects, combined to a buffer, has to be a power of two (2, 4, 8 etc.) and the buffer base address has to be an integer multiple of the buffer length (e.g. a buffer containing 8 messages can use object 0, 8, 16 or 24 as base object as illustrated in Table 22-2). A base object is defined by setting bitfield MMC to `010' in control register MSGFGCRn and the requested buffer size is determined by selecting an appropriate value for FSIZE. A slave object is defined by setting bitfield MMC to `011'. Bitfield FSIZE has to be equal in all FIFO elements in the same FIFO. User's Manual TwinCAN_X1, V2.1 22-24 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Table 22-2 Message Objects Providing FIFO Base Functionality 0 X X X X X 2 X - - - - 4 X X - - - 6 X - - - - 8 X X X - - 10 X - - - - 12 X X - - - 14 X - - - - 16 X X X X - 18 X - - - - ... 30 X - - - - Msg. Object n > FIFO Size 2 stage FIFO 4 stage FIFO 8 stage FIFO 16 stage FIFO 32 stage FIFO The identifiers and corresponding acceptance masks have to be identical in all FIFO elements belonging to the same buffer in case of a receive FIFO (DIR = `0'). In case of a transmit FIFO (DIR = `1') the identifier of the currently addressed message object is taken into account for transmission. Each member of a buffer configuration keeps its individual MSGVAL, NEWDAT, CPUUPD or MSGLST, TXRQ and RMTPND flag and its separate interrupt control configuration. Inside a FIFO buffer, all elements must be * * * * * * assigned to the same CAN node (control bit NODE in register MSGCFGn), programmed for the same transfer direction (control bit DIR), set up to the same identifier length (control bit XTD), programmed to the same FIFO length (bitfield FSIZEn) and set up with the same value for the FIFO direction (bit FD in register MSGFGCRn). The slave's CANPTR has to point to the FIFO base object. The base object's CANPTR has to be initialized with the message number of the base object, the CANPTR pointers of the slave objects have to be set up with the message number of the base object. The CANPTR of the base object addresses the next FIFO element to be accessed for information transfer and its value can be calculated according the following rule: CANPTRn(new) := CANPTRn(old) & FSIZEn | (CANPTRn(old) + 1) & FSIZEn Control bit FD defines which transfer action (reception or transmission) leads to an update of the CANPTR bitfield. Bit FD works independently from the direction bit DIR of the FIFO elements. The reception of a data frame (DIR = `0') or the reception of a remote frame (DIR = `1') are receive actions leading to an update of CANPTR if FD = `0'. The transmission of a data frame (DIR = `1') or the transmission of a remote frame (DIR = `0') are transmit actions initiating an increment of CANPTR if FD = `1'. Note: The overall message object storage size is not affected by the configuration of buffer structures. The available storage size may be used for 32 message objects without buffering or for one message object with a buffer depth of 32 elements. Additionally, any combination of buffered and unbuffered message objects User's Manual TwinCAN_X1, V2.1 22-25 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module according to the FIFO rules is allowed as long as the limit of 32 message objects is not exceeded. 22.1.5.1 Buffer Access by the CAN Controller The data transfer between the message buffer and the CAN bus is managed by the associated CAN controller. Each buffer is controlled by a FIFO algorithm (First In, First Out = First Overwritten) storing messages, delivered by the CAN controller, in a circular order. CAN Pointer = base + 1 (slave) Element 1 CAN Pointer = base + 0 Element 0 (base) (slave) Element 7 CAN Pointer = base + 7 Element 6 (slave) CAN Pointer = base + 6 Element 5 (slave) (slave) Element 2 CAN Pointer = base + 2 Element 3 (slave) (slave) Element 4 CAN Pointer = base + 3 CAN Pointer = base + 4 CAN Pointer = base + 5 MCA05484 Figure 22-14 Structure of a FIFO Buffer with one Base Object and Seven Slave Objects If the FIFO buffer was initialized with receive objects, the first accepted message is stored in the base message object (number n), the second message is written to buffer element (n+1) and so on. The number of the element, used to store the next input message, is indicated by bitfield CANPTR in control register MSGFGCRn of the base object. If the reserved buffer space has been used up, the base message object (followed by the consecutive slave objects) is addressed again to store the next incoming message. When a message object was not read out on time by the CPU, the previous User's Manual TwinCAN_X1, V2.1 22-26 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module message data is overwritten, which is indicated by flag MSGLST in the corresponding MSGCTR register. If the FIFO buffer was initialized with transmit message objects, the CAN controller starts the transfer with the contents of buffer element 0 (FIFO base object) and increments bitfield CANPTR in control register MSGFGCRn, pointing to the next element to be transmitted. If the message object, which is currently addressed by the base object's CANPTR, is not valid (MSGVAL = `01'), the FIFO is not enabled for data transfer. In this case, the MSGVAL bitfields of the other FIFO elements (including the base element if not currently addressed) are not taken into account. In the case that the MSGVAL bitfields are set to `10' for the FIFO base object and `01' for the currently addressed FIFO slave object, the data will not be delivered to the slave object, whereas the bitfield CANPTR in the FIFO base object is incremented according to FIFO rules. If the FIFO is set up for the transmission of data frames and a matching remote frame is detected for one of the elements of the FIFO, the transmit request and remote pending bits will be set automatically in the corresponding message object. The transmission of the requested data frame is handled according to the FIFO rules and the value of the CANPTR bitfield in the FIFO base object. 22.1.5.2 Buffer Access by the CPU The message transfer between a buffer and the CPU has to be managed by software. All message objects, combined to a buffer, can be accessed directly by the CPU. Bitfield CANPTR in control register MSGFGCRn is not automatically modified by a CPU access to the message object registers. User's Manual TwinCAN_X1, V2.1 22-27 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.6 Gateway Message Handling The CAN module supports an automatic information transfer between two independent CAN bus systems without CPU interaction. CAN Bus A CAN Bus B CAN Node A Gateway CAN Node B CAN Message Object Memory Bus Interface CPU MCA05485 Figure 22-15 TwinCAN Gateway Functionality The gateway functionality is handled via the CAN message object memory shared by both CAN nodes. Each object stored in the message memory is associated to node A or to node B via bit NODE in the message configuration register MSGCFGn. The information exchange between both CAN nodes can be handled by coupling two message objects (normal gateway mode) or by sharing one common message object (shared gateway mode). In the following paragraphs, the gateway side receiving data frames is named "source" (indicated by User's Manual TwinCAN_X1, V2.1 22-28 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module To FIFO Object n To FIFO Object n + 1 To FIFO Object n + 2 To FIFO Object n + 3 Source Bus Speed A Message 1 Message 2 Message 3 Message 4 Node A TwinCAN Node B Destination Bus Speed B Message 1 Message 2 Message 3 Message 4 To FIFO Object n To FIFO Object n + 1 To FIFO Object n + 2 To FIFO Object n + 3 MCA05486 Figure 22-16 Message Burst in Case of FIFO/Gateway 22.1.6.1 Normal Gateway Mode The normal gateway mode consumes two message objects to transfer a message from the source to the destination node. In this mode, different identifiers can be used for the same message data. Details of the message transfer through the normal gateway are controlled by the respective MSGFGCR 22-29 V2.0, 2004-04 User's Manual TwinCAN_X1, V2.1 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module * When bit IDC * * The destination message object, addressed by CANPTR * * * User's Manual TwinCAN_X1, V2.1 22-30 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module MMC Source CAN Bus Destination CAN Bus Gateway Source Gateway Gateway Destination Node = Pointer to Destination Message Object Node = Pointer to Destination Message Object Copy Copy if IDC Set if RXIE Copy Data Frame Data Frame (GDFS MCA05487 Figure 22-17 Data Frame Reception in Normal Gateway Mode with a Standard Destination Message Object (MMC User's Manual TwinCAN_X1, V2.1 22-31 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module MMC Source CAN Bus Destination CAN Bus Gateway Source Gateway Gateway Destination Pointer to Source Message Object Node = Pointer to Destination Message Object Node = MCA05488 Copy if IDC Set if RXIE Updated if RMM Remote Request (SRREN Figure 22-18 Remote Frame Transfer in Normal Gateway Mode, MMC User's Manual TwinCAN_X1, V2.1 22-32 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.6.2 Normal Gateway with FIFO Buffering MMC User's Manual TwinCAN_X1, V2.1 22-33 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Source CAN Bus Destination CAN Bus Gateway Source Gateway Gateway Destination Node = MMC CANPTR MMC Pointer to Base Object CANPTR MCA05489 FIFO Copy Remote Request by SW (CPUUPD Figure 22-19 Data Frame Transfer in Normal Gateway Mode with a 2 Stage FIFO on the Destination Side (MMC User's Manual TwinCAN_X1, V2.1 22-34 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module frame with matching identifier should initiate an interrupt service request for the addressed FIFO message object. The associated interrupt service routine may copy the message identifier and the data length code from the received remote frame to a receive message object linked with the source side CAN node. In any case, TXRQ of the selected receive message object must be set to `10' initiating the transmission of a remote frame on the source side. Source CAN Bus Destination CAN Bus Gateway Source Gateway Gateway Destination Node = MMC CANPTR MMC Pointer to Base Object CANPTR Copy Data Frame Data Frame (GDFS MCA05490 Figure 22-20 Remote Frame Transfer in Normal Gateway Mode with a 2-stage FIFO on the Destination Side User's Manual TwinCAN_X1, V2.1 22-35 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.6.3 Shared Gateway Mode In shared gateway mode, only one message object is required to implement a gateway functionality. The shared gateway object can be considered as normal message object, which is toggled between the source and destination CAN node as illustrated in Figure 22-21. Source CAN Bus Destination CAN Bus Source Node Destination Node Shared Gateway Control Logic Node = Pointer to Message Object MCA05491 Figure 22-21 Principle of the Shared Gateway Mode Each message object can be used as shared gateway by setting MMC in the corresponding MSGFGCRn register to `101'. When the message configuration bit NODE is cleared, CAN node A is used as source, transferring data frames to destination node B. If NODE is set to `1', CAN node B operates as data source. A bidirectional gateway is achieved by using a second message object, configured to shared gateway mode with a complementary NODE declaration. Bitfield CANPTR has to be initialized with the shared gateway's message object number, whereas FSIZE, IDC and DLCC have to be cleared. Bit GDFS in control register MSGFGCRn determines, whether bit TXRQ will be automatically set in case of an arriving data frame with matching identifier (GDFS = `1'). User's Manual TwinCAN_X1, V2.1 22-36 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Bit SRREN determines, whether a remote frame, received on the destination side, is transferred through the gateway to the source node or is directly answered by a data frame generated on the destination side. The functionality of the shared gateway mode is optimized to support different scenarios: * a data source, connected with CAN node A, transmits continuously data frames, which have to be automatically emitted on the destination CAN bus by CAN node B. The corresponding transfer state transitions are 1 - 2 - ... a data source, connected with CAN node A, transmits continuously data frames, which have to be emitted by CAN node B upon a matching remote frame received from the destination CAN bus. The corresponding transfer state transitions are 7 - 4 - 2 - ... a data source, connected with CAN node A, transmits a data frame upon a matching remote frame, which has been triggered by a matching remote frame received by CAN node B. The respective data frame has to be emitted again on the destination CAN bus by CAN node B. The corresponding transfer state transitions are 5 - 6 - 1 - 3 - ... * * Depending on the application, the shared gateway message object can be initialized as receive object on the source side or transmit object on the destination side via an appropriate configuration of NODE, DIR, GDFS and SRREN. The various transfer states are illustrated in Figure 22-22. Data Frame Transmission, SRREN = `1' 3 Transmit Object Destination Side TXRQ Set 4 Remote Frame Reception, SRREN = `0' 7 Data Frame Reception, GDFS = `0' Transmit Object Destination Side TXRQ Reset 1 Data Frame Reception, GDFS = `1' 2 Data Frame Transmission, SRREN = `0' 5 Remote Frame Reception, SRREN = `1' Receive Object Source Side TXRQ Reset 6 Remote Frame Transmission Receive Object Source Side TXRQ Set MCA05492 Figure 22-22 Transfer States in Shared Gateway Mode User's Manual TwinCAN_X1, V2.1 22-37 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module When a shared gateway message object, set up as receive object on the source side (lower left state bubble in Figure 22-22), receives a data frame while GDFS is set to `1', it commutes to a transmission object on the destination side by toggling control bits NODE and DIR and sends the corresponding data frame without any CPU interaction (upper left state bubble). Depending on control bit SRREN, the shared gateway message object returns to its initial function as receive object assigned to the source side (SRREN = `0': state transition 2 to the lower left state bubble in Figure 22-22) or remains assigned to the destination side waiting for a remote frame with matching identifier (SRREN = `1': state transition 3 to the upper right state bubble). When the shared gateway message object is assigned as transmit object to the destination side (upper right state bubble), it responds to remote frames received on the destination side. If bit SRREN is cleared, the remote request is directly answered by a data frame based on the contents of the gateway message object (state transition 4 to the upper left state bubble). If bit SRREN is set and a remote frame is received on the destination side, the shared gateway message object commutes to a receive object on the source side by toggling control bits NODE and DIR and prepares the emission of the received remote frame by setting TXRQ and RMTPND to `10' (state transition 5 to the lower right state bubble). Then the shared gateway message object emits the corresponding remote frame without any CPU interaction (state transition 6 to the lower left state bubble). The gateway message object remains assigned to the source side until a data frame with matching identifier arrives (lower left state bubble). Then the shared gateway message object returns to the destination side and, depending on control bit GDFS, transmits immediately the corresponding data frame (GDFS = `1', upper left state bubble) or waits upon an action of the CPU setting TXRQ to `10' (GDFS = `0': state transition 7 to the upper right state bubble). Alternatively, a remote frame with matching identifier, arriving on the destination side, may set TXRQ to `10' and initiate the data frame transmission. If a data frame arrives on the source side while the shared gateway object with matching identifier is switched to the destination side, the data frame on the source side gets lost. Due to the temporary assignment to the destination node, the shared gateway message object does not notice the data frame on the source node and is not able to report the data loss via control bitfield MSGLST = `10'. The probability for a data loss is enlarged, if the automatic data frame transmission on the destination side is disabled by GDFS = `0'. A corresponding behavior has to be taken into account for incoming remote frames on the destination bus. Note: As long as bitfield MSGLST is activated, an incoming data frame cannot be automatically transmitted on the destination side. Due to the internal toggling of control bit DIR, the shared gateway object converts from receive to transmit operation and bitfield MSGLST is interpreted as CPUUPD = `10' preventing the automatic transmission of a data frame. User's Manual TwinCAN_X1, V2.1 22-38 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Impact of the transfer state transitions on the bitfields in the message object in shared gateway mode: Table 22-3 Bitfields Shared Gateway State Transitions (Part 1 of 2) Transition 1: Data Frame Received, GDFS = `1' toggled to Node DIR DATA Identifier DLC TXRQ RMTPND NEWDAT INTPND set if RXIE = `10' set if TXIE = `10' set if TXIE = `10' set if RXIE = `10' Table 22-4 Bitfields Shared Gateway State Transitions (Part 2 of 2) Transition 5: Remote Frame Received, SRREN = `1' toggled to Node DIR DATA Identifier DLC TXRQ RMTPND NEWDAT INTPND User's Manual TwinCAN_X1, V2.1 22-39 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.7 Programming the TwinCAN Module A software initialization should be performed by setting bit INIT in the CAN node specific control register ACR/BCR to `1'. While bit INIT is set, all message transfers between the CAN controller and the CAN bus are disabled. The initialization routine should process the following tasks: * * configuration of the corresponding node, initialization of each associated message object. 22.1.7.1 Configuration of CAN Node A/B Each CAN node can be individually configured by programming the associated register. Depending on the content of the ACR/BCR control registers, the normal operation mode or the CAN analyzer mode is activated. Furthermore, various interrupt categories (status change, error, last error) can be enabled or disabled. The bit timing is defined by programming the ABTR/BBTR register. The prescaler value, the synchronization jump width and the time segments, arranged before and after the sample point, depend on the characteristic of the CAN bus segment linked to the corresponding CAN node. The global interrupt node pointer register (AGINP/BGINP) controls multiplexer connecting an interrupt request source (error, last error, global transmit/receive and frame counter overflow interrupt request) with one of the eight common interrupt nodes. The contents of the INTID mask register (AIMR0/4 and BIMR0/4) decides which interrupt sources may be reported by the AIR/BIR interrupt pending register. 22.1.7.2 Initialization of Message Objects The message memory space, containing 32 message objects, is shared by both CAN nodes. Each message object has to be configured concerning its target node and operation properties. An initialization of the message object properties is always started with disabling the message object via MSGVAL = `01'. The CAN node, associated with a message, is defined by bit NODE in register MSGCFGn. The message object can be also defined as gateway, transferring information from CAN node A to B or vice versa. In this case, the FIFO/Gateway control register MSGFGCRn must be programmed to specify the gateway mode (bitfield MMC), the target interrupt node and further details of the information handover. The identifier, correlated with a message, is set up in register MSGARn. Bit XTD in register MSGCFGn indicates, whether an extended 29-bit or a standard 11-bit identifier is used and has to be set accordingly. Incoming messages can be filtered by the mask defined in register MSGAMRn. The message interrupt handling can be individually configured for transmit and receive direction. The direction specific interrupt is enabled by bits TXIE and RXIE in register MSGCNTn and the target interrupt node is selected by bitfields TXINP and RXINP in User's Manual TwinCAN_X1, V2.1 22-40 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module register MSGCFGn. Message objects can be provided with a FIFO buffer. The buffer size is determined by bitfield FSIZE in the FIFO/Gateway control register MSGFGCRn. For transmit message objects, the object property assignment can be already finished by setting MSGVAL to `10', before the corresponding data partition has been initialized. If bitfield CPUUPD is set to `10', an incoming remote frame with matching identifier is kept in mind via setting TXRQ internally, but is not immediately answered by a corresponding data frame. The message data, stored in register MSGDRn0/MSGDRn4, can be updated as long as CPUUPD is hold on `10'. As soon as CPUUPD is reset to `01', the respective data frame is transmitted by the associated CAN node controller. 22.1.7.3 Controlling a Message Transfer Figure 22-23 illustrates the handling of a transmit message object. The initialization of the message object properties is always started with disabling the message object via MSGVAL = `01'. After resetting some control flags (INTPND, RMTPND, TXRQ and NEWDAT), the transfer direction and the identifier are defined. The message object initialization is finished by setting MSGVAL to `10'. An update of a transmit message data partition should be prepared by setting CPUUPD to `10' followed by a write access to the MSGDRn0/MSGDRn4 register. The data partition update must be indicated by the CPU via setting NEWDAT to `10'. Afterwards, bit CPUUPD must be reset to `01', if an automatic message handling is requested. In this case, the data transmission is started, when flag TXRQ in register MSGCTRn has been set to `10' by software or by the respective CAN node hardware due to a received remote frame with matching identifier. If CPUUPD remains set, the CPU must initiate the data transmission by setting TXRQ to `10' and disabling CPUUPD. If a remote frame with an accepted identifier arrives during the update of a message object's data storage, bit TXRQ and RMTPND are automatically set to `10' and the transmission of the corresponding data frame is automatically started by the CAN controller when CPUUPD is reset again. Figure 22-24 demonstrates the handling of a receive message object. The initialization of the message object properties is embedded between disabling and enabling the message object via MSGVAL as described above. After setting MSGVAL to `10', the transmission of a remote frame can be initiated by the CPU via TXRQ = `10'. The reception of a data frame is indicated by the associated CAN node controller via NEWDAT = `10'. The processing of the received data frame, stored in register MSGDRn0/MSGDRn4, should be started by the CPU with resetting NEWDAT to `01'. After scanning flag MSGLST, indicating a loss of the previous message, the received information should be copied to an application data buffer in order to release the message object for a new data frame. Finally, NEWDAT should be checked again to ensure, that the processing was based on a consistent set of data and not on a part of an old message and part of the new message. User's Manual TwinCAN_X1, V2.1 22-41 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Power Up (all bits written with reset values) Message Initialization MSGVAL = `01' INTPND := `01' RMTPND := `01' TXRQ := `01' NEWDAT := `01' DIR := `1' (transmit object) Identifier := (application specific) XTD := (application specific) TXIE := (application specific) RXIE := (application specific) CPUUPD := `10' MSGVAL := `10' Update : Start CPUUPD := `10' NEWDAT := `10' Update Write / Calculate Message Contents Update : End CPUUPD := `01' yes TXRQ := `10' Want to Send ? no no `01' : Reset `10' : Set Update Message ? yes MCA05493 Figure 22-23 CPU Handling of Message Objects with Direction = Transmit User's Manual TwinCAN_X1, V2.1 22-42 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Power Up (all bits written with reset values) Initialization MSGVAL = `01' INTPND := `01' RMTPND := `01' TXRQ := `01' NEWDAT := `01' DIR := 0 (receive object) MSGLST := `01' TXIE := (application specific) RXIE := (application specific) Identifier := (application specific) XTD := (application specific) MSGVAL := `10' NEWDAT := `01' Data Frame Processing Process Message Contents NEWDAT = `10' ? no yes Restart Process no Remote Frame Transmission ? yes Remote Frame Generation TXRQ := `10' `01' : Reset `10' : Set MCA05494 Figure 22-24 CPU Handling of Message Objects with Direction = Receive User's Manual TwinCAN_X1, V2.1 22-43 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.8 Loop-Back Mode The TwinCAN module's loop-back mode provides the means to internally test the TwinCAN module and CAN driver software. CAN driver software can be developed and tested without being connected to a CAN bus system. In loop-back mode, the transmit pins deliver recessive signals to the transceiver. The transmit signals are combined together and are connected to the internal receive signals, as shown in Figure 22-25. The receive input pins are not taken into account in loop-back mode. MUX RxDCA 0 1 TwinCAN Kernel MUX MUX 1 0 1 TxDCA RxDCB 0 1 & 1 MUX 0 1 TxDCB LBM MCA05495 Figure 22-25 Loop-back Mode Loop-back mode is controlled by bits LBM in the bit timing registers of Node A and Node B according to Table 22-5. Table 22-5 ABTR.LBM 0 0 1 1 Loop-Back Mode BBTR.LBM 0 1 0 1 Description Loop-back mode is disabled. Loop-back mode is disabled. Loop-back mode is disabled. Loop-back mode is enabled. User's Manual TwinCAN_X1, V2.1 22-44 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.9 Single Transmission Try Functionality Single transmission try functionality is controlled individually for each message object by bit STT in register MSGFGCRn. If the single transmission try functionality is enabled, the transmit request flag TXRQ is reset immediately after the transmission of a frame related to this message object has started. Thus, a transmit frame is only transferred once on the CAN bus, even if it has been corrupted by error frames. Note: A message object must be tagged valid by bitfield MSGVAL in order to enable the transmission of the respective frame. User's Manual TwinCAN_X1, V2.1 22-45 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.1.10 Module Clock Requirements The functionality of the TwinCAN module is programmable in several respects. In order to operate at a specific baudrate with a given functionality a certain minimum module clock frequency is required. Table 22-6 lists some examples for certain configurations. These examples cover the worst case conditions where the CPU executes accesses to the TwinCAN module consecutively and with maximum speed. The module clock frequency can be reduced (see last column of Table 22-6) if no frames without data (data frames with DLC = 0 or remote frames) are transferred over the CAN bus. This is possible, because internal operations can be executed while the data part is transferred. Table 22-6 Minimum Module Clock Frequencies for 1 Mbit/s 1 Node Active, DLC 0 FIFO/gateway enabled No FIFO/gateway 21 MHz 20 MHz 2 Nodes Active, DLC 0 36 MHz 29 MHz 2 Nodes Active, DLC 1 32 MHz 26 MHz Note: The given numbers are required for the maximum CAN bus speed of 1 Mbit/s. For lower bit-rates the minimum module clock frequency can be reduced linearly, i.e. half the frequency is required for a bit-rate of 500 kbit/s. However, if two nodes are operated with different bit-rates, the module clock frequency must be chosen according to the fastest node. User's Manual TwinCAN_X1, V2.1 22-46 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.2 22.2.1 TwinCAN Register Description Register Map Figure 22-26 shows all registers associated with the TwinCAN module kernel. CAN Node A Registers ACR ASR AIR ABTR AGINP AFCR AIMR0 AIMR4 AECNT CAN Node B Registers BCR BSR BIR BBTR BGINP BFCR BIMR0 BIMR4 BECNT CAN Message Object Registers 1) MSGDRn0 MSGDRn4 MSGARn MSGAMRn MSGCTRn MSGCFGn MSGFGCRn Global CAN Control / Status Registers RXIPND TXIPND ACR ASR AIR ABTR AGINP AFCR AIMR0 AIMR4 AECNT MSGDRn0 MSGARn MSGCTRn MSGFGCRn RXIPND Node A Control Register Node A Status Register Node A Interrupt Pending Register Node A Bit Timing Register Node A Global Int. Node Pointer Reg. Node A Frame Counter Register Node A INTID Mask Register 0 Node A INTID Mask Register 4 Node A Error Counter Register Msg. Object n Data Register 0 Msg. Object n Arbitration Register Msg. Object n Control Register Msg. Object n FIFO/Gatew. Cont. Reg. Receive Interrupt Pending Register BCR BSR BIR BBTR BGINP BFCR BIMR0 BIMR4 BECNT Node B Control Register Node B Status Register Node B Interrupt Pending Register Node B Bit Timing Register Node B Global Int. Node Pointer Reg. Node B Frame Counter Register Node B INTID Mask Register 0 Node B INTID Mask Register 4 Node B Error Counter Register MSGDRn4 Msg. Object n Data Register 4 MSGAMRn Msg. Object n Acceptance Mask Reg. MSGCFGn Msg. Object n Configuration Register TXIPND Transmit Interrupt Pending Register 1) The number `n' indicates the message object number, n = 0 ... 31. MCA05496 Figure 22-26 TwinCAN Kernel Registers User's Manual TwinCAN_X1, V2.1 22-47 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Module Offset +000H Reserved +200H CAN Node A Registers +240H CAN Node B Registers +280H Global Control Registers +2C0H Reserved +300H Message Object 0 +320H Message Object 1 +340H Message Object 2 ... Data Register 0 Data Register 4 Arbitration Register Acceptance Mask Reg. Message Control Reg. Message Object 31 Message Config. Reg. FIFO/Gateway Control +00H +04H +08H +0CH +10H +14H +18H MCA05497 Control Reg. Status Reg. Interrupt Pending Reg. Bit Timing Reg. Node A Global INP Reg. Frame Counter Reg. INTID Mask 0 Reg. INTID Mask 4 Reg. Error Counter Reg. Control Reg. Status Reg. Node B Interrupt Pending Reg. Bit Timing Reg. Global INP Reg. Frame Counter Reg. INTID Mask 0 Reg. INTID Mask 4 Reg. Error Counter Reg. +00H +04H +08H +0CH +10H +14H +18H +1CH +20H +00H +04H +08H +0CH +10H +14H +18H +1CH +20H Receive Int. Pending Transmit Int. Pending +04H +08H Message Object n ... +6E0H Figure 22-27 TwinCAN Kernel Address Map User's Manual TwinCAN_X1, V2.1 22-48 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.2.2 CAN Node A/B Registers The Node Control Register controls the initialization, defines the node specific interrupt handling and selects an operation mode. ACR Node A Control Register BCR Node B Control Register 15 14 13 12 0 r 11 10 9 8 7 6 5 0 r 4 Reset Value: 0001H Reset Value: 0001H 3 2 SIE rw 1 0 r 0 INIT rwh CAL CCE M rw rw LEC EIE IE rw rw Field INIT Bits 0 Type Description rwh Initialization 0 Resetting bit INIT starts the synchronization to the CAN bus. After a synchronization procedure1), the node takes part in CAN communication. 1 After setting bit INIT, the CAN node stops all CAN bus activities and all registers can be initialized without any impact on the actual CAN bus traffic. Bit INIT is automatically set when the bus-off state is entered. Status Change Interrupt Enable A status change interrupt occurs when a message transfer (indicated by the flags TXOK or RXOK in the status registers ASR or BSR) is successfully completed. 0 Status change interrupt is disabled. 1 Status change interrupt is enabled. Error Interrupt Enable An error interrupt is generated on a change of bit BOFF or bit EWRN in the status registers ASR or BSR. 0 Error interrupt is disabled. 1 Error interrupt is enabled. SIE 2 rw EIE 3 rw User's Manual TwinCAN_X1, V2.1 22-49 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field LECIE Bits 4 Type Description rw Last Error Code Interrupt Enable A last error code interrupt is generated when an error code is set in bitfield LEC in the status registers ASR or BSR. 0 Last error code interrupt is disabled. 1 Last error code interrupt is enabled. Configuration Change Enable 0 Access to bit timing register and modification of the error counters are disabled. 1 Access to bit timing register and modification of the error counters are enabled. CAN Analyzer Mode Bit CALM defines if the message objects of the corresponding node operate in analyzer mode. 0 The CAN message objects participate in CAN protocol. 1 CAN Analyzer Mode is selected. Reserved; returns `0' if read; should be written with `0'. CCE 6 rw CALM 7 rw 0 1, 5, [15:8] r 1) After resetting bit INIT by software without being in the bus-off state (e.g. after power-on), a sequence of 11 consecutive recessive bits (11 x `1') on the bus has to be monitored before the module takes part in the CAN traffic. During a bus-off recovery procedure, 128 sequences of 11 consecutive recessive bits (11 x `1') have to be detected. The monitoring of the recessive bit sequences is immediately started by hardware after entering the bus-off state. The number of already detected 11 x `1' sequences is indicated by the receive error counter. At the end of the bus-off recovery sequence, bit INIT is tested by hardware. If INIT is still set, the affected CAN node controller waits until INIT is cleared and 11 consecutive recessive bits (11 x `1') are detected on the CAN bus, before the node takes part in CAN traffic again. If INIT has been already cleared, the message transfer between the affected CAN node controller and its associated CAN bus is immediately enabled. User's Manual TwinCAN_X1, V2.1 22-50 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Node Status Register reports error states and successfully ended data transmissions. This register has to be read in order to release the status change interrupt request. ASR Node A Status Register BSR Node B Status Register 15 14 13 12 0 r 11 10 9 8 7 6 5 0 r 4 RX OK rwh Reset Value: 0000H Reset Value: 0000H 3 TX OK rwh 2 1 LEC rwh 0 B E OFF WRN rh rh Field LEC Bits [2:0] Type Description rwh Last Error Code Bitfield LEC indicates if the latest CAN message transfer has been correct (No Error) or it indicates the type of error, which has been detected. The error conditions are detailed in Table 22-7. 000 No Error 001 Stuff Error 010 Form Error 011 Ack Error 100 Bit1 Error 101 Bit0 Error 110 CRC Error 111 reserved Message Transmitted Successfully 0 No successful transmission since last flag reset. 1 A message has been transmitted successfully (error free and acknowledged by at least one other node). TXOK must be reset by software. Message Received Successfully 0 No successful reception since last flag reset. 1 A message has been received successfully. RXOK must be reset by software. TXOK 3 rwh RXOK 4 rwh User's Manual TwinCAN_X1, V2.1 22-51 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field EWRN Bits 6 Type Description rh Error Warning Status 0 No warning limit exceeded. 1 One of the error counters in the Error Management Logic reached the error warning limit of 96. Bus-Off Status 0 CAN controller is not in the bus-off state. 1 CAN controller is in the bus-off state. Reserved; returns `0' if read; should be written with `0'. BOFF 7 rh 0 5, [15:8] r Table 22-7 LEC Error No Error Stuff Error Form Error Ack Error Bit1 Error Meaning of the LEC Bitfield Description The latest transfer on the CAN bus has been completed successfully. More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. A fixed format part of a received frame has the wrong format. The transmitted message was not acknowledged by another node. During a message transmission, the CAN node tried to send a recessive level (`1'), but the monitored bus value was dominant (outside the arbitration field and the acknowledge slot). Two different conditions are signaled by this code: 1. During transmission of a message (or acknowledge bit, active error flag, overload flag), the CAN node tried to send a dominant level (`0'), but the monitored bus value has been recessive. 2. During bus-off recovery, this code is set each time a sequence of 11 recessive bits has been monitored. The CPU may use this code as an indication, that the bus is not continuously disturbed. The CRC checksum of the received message was incorrect. Bit0 Error CRC Error User's Manual TwinCAN_X1, V2.1 22-52 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Interrupt Pending Register contains the identification number of the pending interrupt request with the highest priority. AIR Node A Interrupt Pending Register BIR Node B Interrupt Pending Register 15 14 13 12 0 r 11 10 9 8 7 6 5 Reset Value: 0000 0000H Reset Value: 0000 0000H 4 3 2 1 0 INTID rwh Field INTID Bits [7:0] Type Description rwh Interrupt Identifier 00H No interrupt is pending. 01H LEC, EI, TXOK or RXOK interrupt is pending. 02H RX or TX interrupt of message object 0 is pending. 03H RX or TX interrupt of message object 1 is pending. ... ... 21H RX or TX interrupt of message object 31 is pending. Bitfield INTID can be written by software to start an update after software actions and to check for changes. Reserved; returns `0' if read. 0 [15:8] r User's Manual TwinCAN_X1, V2.1 22-53 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register AECNT/BECNT contains the values of the receive error counter and the transmit error counter. Some additional status/control bits allow for easier error analysis. AECNTH Node A Error Counter Register High AECNTL Node A Error Counter Register Low BECNTH Node B Error Counter Register High BECNTL Node B Error Counter Register Low 15 14 13 0 r 15 14 13 12 11 10 12 11 10 9 LE INC rh 9 8 LE TD rh 8 7 6 5 4 REC rwh 7 6 5 4 Reset Value: 0060H Reset Value: 0000H Reset Value: 0060H Reset Value: 0000H 3 2 1 0 EWRNLVL rw 3 2 1 0 TEC rwh Field REC Bits [7:0] Low [15:8] Low [7:0] Low Type Description rwh Receive Error Counter Bitfield REC contains the value of the receive error counter for the corresponding node. Transmit Error Counter Bitfield TEC contains the value of the transmit error counter for the corresponding node. Error Warning Level Bitfield EWRNLVL defines the threshold value (warning level, default 60H = 96D) to be reached in order to set the corresponding error warning bit EWRN. TEC rwh EWRNLVL rw User's Manual TwinCAN_X1, V2.1 22-54 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field LETD Bits 8 High Type Description rh Last Error Transfer Direction 0 The last error occurred while the corresponding CAN node was receiving a message (REC has been incremented). 1 The last error occurred while the corresponding CAN node was transmitting a message (TEC has been incremented). An error during message reception is indicated without regarding the result of the acceptance filtering. Last Error Increment 0 The error counter was incremented by 1 due to the error reported by LETD. 1 The error counter was incremented by 8 due to the error reported by LETD. Reserved; returns `0' if read; should be written with `0'. LEINC 9 High rh 0 [15:10] r High Note: Modifying the contents of register AECNT/BECNT requires bit CCE = `1' in register ACR/BCR. User's Manual TwinCAN_X1, V2.1 22-55 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Bit Timing Register contains all parameters to adjust the data transfer baud rate and the bit timing. ABTRH Node A Bit Timing Register High ABTRL Node A Bit Timing Register Low BBTRH Node B Bit Timing Register High BBTRL Node B Bit Timing Register Low 15 14 13 12 11 10 9 8 0 r 15 DIV 8X rw 14 13 TSEG2 rw 12 11 10 9 8 7 6 5 4 3 BRP rw 2 1 7 6 5 4 Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H 3 2 1 0 LBM rw 0 TSEG1 rw SJW rw Field BRP Bits [5:0] Low Type Description rw Baudrate Prescaler One bit time quantum corresponds to the period length of the external oscillator clock multiplied by (BRP+1), depending also on bit DIV8X. (Re)Synchronization Jump Width (SJW+1) time quanta are allowed for resynchronization. Time Segment Before Sample Point (TSEG1+1) time quanta before the sample point take into account the signal propagation delay and compensate a mismatch between transmitter and receiver clock phase. Valid values for TSEG1 are 2 ... 15. SJW [7:6] Low [11:8] Low rw TSEG1 rw User's Manual TwinCAN_X1, V2.1 22-56 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field TSEG2 Bits [14:12] Low Type Description rw Time Segment After Sample Point (TSEG2+1) time quanta after the sample point take into account a user defined delay and compensate a mismatch between transmitter and receiver clock phase. Valid values for TSEG2 are 1 ... 7. Division of Module Clock fCAN by 8 0 The baudrate prescaler is directly driven by fCAN. 1 The baudrate prescaler is driven by fCAN/8. Loop-Back Mode 0 Loop-back mode is disabled. 1 Loop-back mode is enabled, if bits LBM are set in the BTR registers of Node A and Node B. Reserved; read as `0'; should be written with `0'. DIV8X 15 Low 0 High rw LBM rw 0 [15:1] High r Note: Modifying the contents of register ABTR/BBTR requires bit CCE = `1' in register ACR/BCR. User's Manual TwinCAN_X1, V2.1 22-57 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Frame Counter Register controls the frame counter functionality and provides status information. AFCRH Node A Frame Counter Register High AFCRL Node A Frame Counter Register Low BFCRH Node B Frame Counter Register High BFCRL Node B Frame Counter Register Low 15 14 13 12 0 r 15 14 13 12 11 10 9 8 CFC rwh 11 10 9 8 7 6 5 0 r 5 4 3 2 4 Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H 3 2 1 0 CFC CFC OV IE rwh 7 rw 6 CFCMD rw 1 0 Field CFC Bits [15:0] Low Type Description rwh CAN Frame Counter This bitfield contains the count value of the frame counter. At the end of a correct message transfer, the value of CFC (captured value during SOF bit) is copied to bitfield CFCVAL of the corresponding message object control register MSGCTRn. User's Manual TwinCAN_X1, V2.1 22-58 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field CFCMD Bits [3:0] High Type Description rw Frame Count Mode This bitfield defines the operation mode of the frame counter. This counter can work on frame base (frame count) or on time base (time stamp). 0XXXB Frame Count:1) 0XX0B The CFC is not incremented after a foreign frame was transferred on the CAN bus. 0XX1B The CFC is incremented each time a foreign frame was transferred correctly on the CAN bus. 0X0XB The CFC is not incremented after a frame was received by the respective CAN node. The CFC is incremented each time a frame 0X1XB was received correctly by the node. 00XXB The CFC is not incremented after a frame was transmitted by the node. 01XXB The CFC is incremented each time a frame was transmitted correctly by the node. 1XXXB Time Stamp: 1000B The CFC is incremented with the beginning of a new bit time. The value is sampled during the SOF bit. 1001B The CFC is incremented with the beginning of a new bit time. The value is sampled during the last bit of EOF. others reserved CAN Frame Count Interrupt Enable Setting CFCIE enables the CAN Frame Counter Overflow (CFCO) interrupt request. 0 The CFCO interrupt is disabled. 1 The CFCO interrupt is enabled. CAN Frame Count Overflow Flag Flag CFCOV is set on a CFC overflow condition (FFFFH to 0000H). An interrupt request is generated if the corresponding interrupt is enabled (CFCIE = `1'). 0 An overflow has not yet been detected. 1 An overflow has been detected since the bit has been reset. CFCOV must be reset by software. CFCIE 6 High rw CFCOV 7 High rwh User's Manual TwinCAN_X1, V2.1 22-59 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field 0 Bits [5:4], [15:8] High Type Description r Reserved; read as `0'; should be written with `0'. 1) If the frame counter functionality has been selected (CFCMD.3 = `0'), bit CFCMD.0 enables or disables the counting of foreign frames. A foreign frame is a correct frame on the bus, which has not been transmitted /received by the node itself. Bit CFCMD.1 enables or disables the counting of frames, which have been received correctly by the corresponding CAN node. Bit CFCMD.2 enables or disables the counting of frames, which have been transmitted correctly by the corresponding CAN node. User's Manual TwinCAN_X1, V2.1 22-60 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Global Interrupt Node Pointer Register connects each global interrupt request source with one of the 8 available CAN interrupt nodes. AGINP Node A Global Interrupt Node Pointer Register BGINP Node B Global Interrupt Node Pointer Register 15 0 r 14 13 CFCINP rw 12 11 0 r 10 9 TRINP rw 8 7 0 r 6 5 LECINP rw 4 Reset Value: 0000H Reset Value: 0000H 3 0 r 2 1 EINP rw 0 Field EINP Bits [2:0] Type Description rw Error Interrupt Node Pointer Number of interrupt node reporting the "Error Interrupt Request", if enabled by EIE = `1'. 000B CAN interrupt node 0 is selected. ... ... 111B CAN interrupt node 7 is selected. Last Error Code Interrupt Node Pointer Number of interrupt node reporting the last error interrupt request, if enabled by LECIE = `1'. 000B CAN interrupt node 0 is selected. ... ... 111B CAN interrupt node 7 is selected. Transmit/Receive OK Interrupt Node Pointer Number of interrupt node reporting the transmit and receive interrupt request, if enabled by SIE = `1'. 000B CAN interrupt node 0 is selected. ... ... 111B CAN interrupt node 7 is selected. Frame Counter Interrupt Node Pointer Number of interrupt node reporting the frame counter overflow interrupt request, if enabled by CFCIE = `1'. 000B CAN interrupt node 0 is selected. ... ... 111B CAN interrupt node 7 is selected. Reserved; read as `0'; should be written with `0'. LECINP [6:4] rw TRINP [10:8] rw CFCINP [14:12] rw 0 3, 7, 11, 15 r User's Manual TwinCAN_X1, V2.1 22-61 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Interrupt Identification Mask Registers allow for disabling the identification notification of a pending interrupt request in the AIR/BIR register. The Interrupt Mask Registers AIMR0/BIMR0 are used to enable the message specific interrupt sources (correct transmission/ reception) for the generation of the corresponding INTID value. AIMRH0 Node A INTID Mask Register 0 High AIMRL0 Node A INTID Mask Register 0 Low BIMRH0 Node B INTID Mask Register 0 High BIMRL0 Node B INTID Mask Register 0 Low 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H 3 2 1 0 IMCn (n = 31-16) rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMCn (n = 15-0) rw Field IMCn (n = 15-0) IMCn (n = 31-16) Bits n Low n-16 High Type Description rw Message Object n INTID Mask Control 0 Message object n is ignored for the generation of the INTID value. 1 The interrupt pending status of message object n is taken into account for the generation of the INTID value. User's Manual TwinCAN_X1, V2.1 22-62 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Interrupt Mask Registers AIMR4/BIMR4 are used to enable the node specific interrupt sources (last error, correct reception, error warning/bus-off) for the generation of the corresponding INTID value. AIMR4 Node A INTID Mask Register 4 BIMR4 Node B INTID Mask Register 4 15 14 13 12 11 10 9 0 r 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 IMC IMC IMC 34 33 32 rw rw rw Field IMC32 Bits 0 Type Description rw Last Error Interrupt INTID Mask Control 0 The last error interrupt source is ignored for the generation of the INTID value. 1 The last error interrupt source is taken into account for the generation of the INTID value. TX/RX Interrupt INTID Mask Control 0 The TX/RX interrupt source is ignored for the generation of the INTID value. 1 The TX/RX interrupt pending status is taken into account for the generation of the INTID value. Error Interrupt INTID Mask Control 0 The error interrupt source is ignored for the generation of the INTID value. 1 The error interrupt pending status is taken into account for the generation of the INTID value. Reserved; read as `0'; should be written with `0'. IMC33 1 rw IMC34 2 rw 0 [15:3] r User's Manual TwinCAN_X1, V2.1 22-63 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.2.3 CAN Message Object Registers Each message object is provided with a set of control and data register. The corresponding register names are supplemented with a variable n running from 0 to 31 (e.g. MSGDRn0 means that data register MSGDR300 is assigned with message object number 30). The Message Data Register 0 contains the data bytes 0 to 3 of message object n. MSGDRHn0 (n = 31-0) Message Object n Data Register 0 High MSGDRLn0 (n = 31-0) Message Object n Data Register 0 Low 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 DATA3 rwh 15 14 13 12 11 10 9 8 7 6 5 DATA2 rwh 4 3 2 1 0 DATA1 rwh DATA0 rwh Field DATA0 DATA1 DATA2 DATA3 Bits [7:0] Low [15:8] Low [7:0] High [15:8] High Type Description rwh rwh rwh rwh Data Byte 0 Associated to Message Object n Data Byte 1 Associated to Message Object n Data Byte 2 Associated to Message Object n Data Byte 3 Associated to Message Object n User's Manual TwinCAN_X1, V2.1 22-64 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Message Data Register 4 contains the data bytes 4 to 7 of message object n. MSGDRHn4 (n = 31-0) Message Object n Data Register 4 High MSGDRLn4 (n = 31-0) Message Object n Data Register 4 Low 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 DATA7 rwh 15 14 13 12 11 10 9 8 7 6 5 DATA6 rwh 4 3 2 1 0 DATA5 rwh DATA4 rwh Field DATA4 DATA5 DATA6 DATA7 Bits [7:0] Low [15:8] Low [7:0] High [15:8] High Type Description rwh rwh rwh rwh Data Byte 4 Associated to Message Object n Data Byte 5 Associated to Message Object n Data Byte 6 Associated to Message Object n Data Byte 7 Associated to Message Object n User's Manual TwinCAN_X1, V2.1 22-65 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register MSGARn contains the identifier of message object n. MSGARHn (n = 31-0) Message Object n Arbitration Register High MSGARLn (n = 31-0) Message Object n Arbitration Register Low 15 14 0 r 15 14 13 12 11 10 9 8 7 13 12 11 10 9 8 7 6 ID[28:16] rwh 6 5 4 3 2 1 0 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 ID[15:0] rwh Field ID[15:0] ID[28:16] 0 Bits [15:0] Low [12:0] High Type Description rwh Message Identifier Identifier of a standard message (ID[28:18]) or an extended message (ID[28:0]). For standard identifiers bits ID[17:0] are "don't care". Reserved; returns `0' if read; should be written with `0'. [15:13] r High User's Manual TwinCAN_X1, V2.1 22-66 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register MSGAMRn contains the mask bits for the acceptance filtering of message object n. MSGAMRHn (n = 31-0) Message Object n Arbitration Mask Register High MSGAMRLn (n = 31-0) Message Object n Arbitration Mask Register Low 15 14 1 r 15 14 13 12 11 10 9 8 7 13 12 11 10 9 8 7 6 AM[28:16] rw 6 5 4 3 2 1 0 5 4 Reset Value: FFFFH Reset Value: FFFFH 3 2 1 0 AM[15:0] rw Field AM[15:0] AM[28:16] Bits [15:0] Low [12:0] High Type Description rw Message Acceptance Mask Mask to filter incoming messages with standard identifiers (AM[28:18]) or extended identifiers (AM[28:0]). For standard identifiers bits AM[17:0] are "don't care". 0 Identifier bit is ignored for acceptance test. 1 Identifier bit is taken into account for the acceptance filtering. Reserved; returns `1' if read; should be written with `1'. 1 [15:13] r High User's Manual TwinCAN_X1, V2.1 22-67 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register MSGCTRn affects the data transfer between a CAN node controller and the corresponding message object n and provides a bitfield to store the captured value of the frame counter. MSGCTRHn (n = 31-0) Message Object n Message Control Register High MSGCTRLn (n = 31-0) Message Object n Message Control Register Low 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 5555H 3 2 1 0 CFCVAL rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMTPND rwh TXRQ rwh MSGLST CPUUPD rwh NEWDAT rwh MSGVAL rwh TXIE rw RXIE rw INTPND rwh Field INTPND Bits [1:0] Low Type Description rwh Message Object Interrupt Pending INTPND is generated by an "OR" operation between the RXIPNDn and TXIPNDn flags (if enabled by TXIE or RXIE). INTPND must be reset by software. Resetting INTPND also resets the corresponding RXIPND and TXIPND flags. 01 No message object interrupt request is pending. 10 The message object has generated an interrupt request. Message Object Receive Interrupt Enable 01 Message object receive interrupt is disabled. 10 Message object receive interrupt is enabled. If RXIE is set, bits INTPND and RXIPND are set after successful reception of a frame. Message Object Transmit Interrupt Enable 01 Message object transmit interrupt is disabled. 10 Message object transmit interrupt is enabled. If TXIE is set, bits INTPND and TXIPND are set after successful transmission of a frame. RXIE [3:2] Low rw TXIE [5:4] Low rw User's Manual TwinCAN_X1, V2.1 22-68 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field MSGVAL 1) Bits [7:6] Low Type Description rwh Message Object Valid The CAN controller only operates on valid message objects. Message objects can be tagged invalid while they are changed or if they are not used at all. 01 Message object is invalid. 10 Message object is valid. New Message Object Data Available 01 No update of message object data occurred. 10 New message object data has been updated. Message Lost (for reception only) 01 No message object data is lost. 10 The CAN controller has stored a new message into the message object while NEWDAT was still set. The previously stored message is lost. MSGLST must be reset by software. CPU Update (for transmission only) Indicates that the corresponding message object can not be transmitted now. The software sets this bit in order to inhibit the transmission of a message that is currently updated by the CPU or to control the automatic response to remote requests. 01 The message object data can be transmitted automatically by the CAN controller. 10 The automatic transmission of the message data is inhibited. Message Object Transmit Request Flag 01 No message object data transmission is requested by the CPU or a remote frame. 10 The transmission of the message object data, requested by the CPU or by a remote frame, is pending. Automatic setting of TXRQ by the CAN node controller can be disabled for Gateway Message Objects via control bit GDFS = `0'. TXRQ is automatically reset, when the message object has been successfully transmitted. If there are several valid message objects with pending transmit requests, the message object with the lowest message number will be transmitted first. NEWDAT2) [9:8] Low rwh MSGLST [11:10] rwh Low CPUUPD3) [11:10] rwh Low TXRQ4) [13:12] rwh Low User's Manual TwinCAN_X1, V2.1 22-69 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field RMTPND Bits Type Description Remote Pending Flag (used for transmit-objects) 01 No remote node request for a message object data transmission. 10 Transmission of the message object data has been requested by a remote node but the data has not yet been transmitted. When RMTPND is set, the CAN node controller also sets TXRQ. RMTPND is automatically reset, when the message object data has been successfully transmitted. Message Object Frame Counter Value CFCVAL contains a copy of the frame counter content valid for the last correct data transmission or reception executed for the corresponding message object. [15:14] rwh Low CFCVAL [15:0] High rwh 1) MSGVAL has to be set from `01' to `10' in order to take into account an update of bits XTD, DIR, NODE and CANPTR. 2) Bit NEWDAT indicates that new data has been written into the data registers of this corresponding message object. For transmit objects, NEWDAT should be set by software and is reset by the respective CAN node controller when the transmission is started. For receive objects, NEWDAT is set by the respective CAN node controller after receiving a data frame with matching identifier. It has to be reset by software. When the CAN controller writes new data into the message object, unused message bytes will be overwritten with non-specified values. Usually, the CPU will clear this bitfield before working on the data and will verify that the bitfield is still cleared once the CPU has finished working to ensure a consistent set of data. For transmit objects, the CPU should set this bitfield along with clearing bitfield CPUUPD. This will ensure that, if the message is actually being transmitted during the time the message is updated by the CPU, the CAN controller will not reset bitfield TXRQ. In this way, TXRQ is only reset once the actual data has been transferred correctly. 3) While bitfield MSGVAL is set (`10') an incoming matching remote frame is taken into account by automatically setting bitfields TXRQ and RMTPND to `10' (independent from bitfield CPUUPD/MSGLST). The transmission of a frame is only possible if CPUUPD is reset (`01'). 4) If a receive object (DIR = `0') is requested for transmission, a remote frame will be sent in order to request a data frame from another node. If a transmit object (DIR = `1') is requested for transmission, a data frame will be sent. Bitfield TXRQ will be reset by the CAN controller along with bitfield RMTPND after the correct transmission of the data frame if bitfield NEWDAT has not been set or after correct transmission of a remote frame. Note: For transmitting frames (remote CPUUPD/MSGLST has to be reset. frames or data frames), bitfield User's Manual TwinCAN_X1, V2.1 22-70 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The control and status element of the message control registers is implemented with two complementary bits (except the frame counter value). This special mechanism allows the selective setting or resetting of a specific element (leaving others unchanged) without requiring read-modify-write cycles. Table 22-8 illustrates how to use these 2-bitfields. Table 22-8 Value of the 2-bitfield 00B 01B 10B 11B Setting/Resetting the Control and Status Element of the Message Control Registers Function on Write reserved Reset element Set element Leave element unchanged Meaning on Read reserved Element is reset Element is set reserved Register MSGCFGn defines the configuration of message object n and the associated interrupt node pointers. Changes of bits XTD, NODE or DIR by software are only taken into account after setting bitfield MSGVAL to `10'. This avoids unintentional modification while the message object is still active by explicitly defining a timing instant for the update. Bits XTD, NODE or DIR can be written while MSGVAL is `01' or `10', the update always takes place by setting MSGVAL to `10'. MSGCFGHn (n = 31-0) Message Object n Message Configuration Register High MSGCFGLn (n = 31-0) Message Object n Message Configuration Register Low 15 14 13 12 11 0 r 15 14 13 12 0 r 11 10 9 8 7 6 DLC rwh 10 9 8 7 6 5 TXINP rw 5 4 4 Reset Value: 0000H Reset Value: 0000H 3 0 r 3 2 2 1 RXINP rw 1 0 0 DIR XTD rwh rw NO RMM DE rwh rw User's Manual TwinCAN_X1, V2.1 22-71 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field RMM Bits 0 Low Type Description rw Transmit Message Object Remote Monitoring Mode 0 Remote Monitoring mode is disabled. 1 Remote Monitoring mode is enabled for this transmit message object. The identifier and DLC code of a remote frame with matching identifier are copied to this transmit message object in order to monitor incoming remote frames. Bit RMM is only available for transmit objects and has no impact for receive objects. Message Object CAN Node Select 0 The message object is assigned to CAN node A. 1 The message object is assigned to CAN node B. Message Object Extended Identifier 0 This message object uses a standard 11-bit identifier. 1 This message object uses an extended 29-bit identifier. Message Object Direction Control 0 The message object is defined as receive object. If TXRQ = `10', a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, the message data is stored in the corresponding MSGDRn0/MSGDRn4 registers. 1 The message object is declared as transmit object. If TXRQ = `10', the respective data frame is transmitted. On reception of a remote frame with matching identifier, RMTPND and TXRQ are set to `10'. Message Object Data Length Code 0000B - 1XXXB DLC contains the number of data bytes associated to the message object. Bitfield DLC may be modified by hardware in Remote Monitoring Mode and in Gateway Mode. NODE 1 Low 2 Low rwh XTD rw DIR 3 Low rwh DLC1) [7:4] Low rwh User's Manual TwinCAN_X1, V2.1 22-72 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field RXINP Bits [2:0] High Type Description rw Receive Interrupt Node Pointer Bitfield RXINP determines which interrupt node is triggered by a message object receive event, if bitfield RXIE in register MSGCTRn is set. 000B CAN interrupt node 0 is selected. ... ... 111B CAN interrupt node 7 is selected. Transmit Interrupt Node Pointer Bitfield TXINP determines which interrupt node is triggered by a message object transmit event, if bitfield TXIE in register MSGCTRn is set. 000B CAN interrupt node 0 is selected. ... ... 111B CAN interrupt node 7 is selected. Reserved; returns `0' if read; should be written with `0'. TXINP [6:4] High rw 0 [15:8] Low 3, [15:7] High r 1) The maximum number of data bytes is 8. A value > 8 written by the CPU, is internally corrected to 8 but the content of bitfield DLC is not updated. If a received data frame contains a data length code value > 8, only 8 bytes are taken into account. A read access to bitfield DLC returns the original value of the DLC field of the received data frame. The FIFO/gateway control register MSGFGCRn contains bits to enable and to control the FIFO functionality, the gateway functionality and the desired transfer actions. User's Manual TwinCAN_X1, V2.1 22-73 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module MSGFGCRHn (n = 31-0) Message Object n FIFO/Gateway Control Register High MSGFGCRLn (n = 31-0) Message Object n FIFO/Gateway Control Register Low 15 14 13 0 r 15 14 13 FD rw 12 0 r 11 DL CC rw 10 IDC rw 12 11 10 9 MMC rw 9 8 7 8 7 6 0 r 6 0 r 5 4 3 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 CANPTR rwh 2 FSIZE rw 1 0 1 0 STT SDT rw rw SRR GD EN FS rw rw Field FSIZE Bits [4:0] Low Type rw Description FIFO Size Control Bitfield FSIZE determines the number of message objects combined to a FIFO buffer. Even numbered message objects may provide FIFO base or slave functionality, while odd numbered message objects are restricted to slave functionality. In gateway mode, FSIZE determines the length of the FIFO on the destination side. 00000B message object n is part of a 1-stage FIFO 00001B message object n is part of a 2-stage FIFO 00011B message object n is part of a 4-stage FIFO 00111B message object n is part of a 8-stage FIFO 01111B message object n is part of a 16-stage FIFO 11111B message object n is part of a 32-stage FIFO else reserved FSIZE = `00000' leads to the behavior of a standard message object (the pointer CANPTR used for this action will not be changed). This value has to be written if a gateway transfer to a single message object (no FIFO) as destination is desired. FSIZE is not evaluated for message objects configured in standard mode, shared gateway mode or FIFO slave functionality. In this case, FSIZE should be programmed to `00000'. User's Manual TwinCAN_X1, V2.1 22-74 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field GDFS Bits 8 Low Type rw Description Gateway Data Frame Send Specifies if a CAN data frame will be automatically generated on the destination side after new data has been transferred via gateway from the source to the destination side. 0 No additional action, TXRQ will not be set on the destination side. 1 The corresponding data frame will be sent automatically (TXRQ of the message object, pointed to by CANPTRn, will be set by hardware). Bit GDFS is only taken into account, if a data frame has been received (DIR SRREN 9 Low rw User's Manual TwinCAN_X1, V2.1 22-75 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field IDC Bits 10 Low Type rw Description Identifier Copy IDC controls the identifier handling during a frame transfer through a gateway. 0 The identifier of the receiving object is not copied to the transmitting message object. 1 The identifier of the receiving object is automatically copied to the transmitting message object. Bitfield IDC is restricted to message objects configured in normal gateway mode. Data Length Code Copy DLCC controls the handling of the data length code during a data frame transfer through a gateway. 0 The data length code, provided by the source object, is not copied to the transmitting object. 1 The data length code, valid for the receiving object, is copied automatically to the transmitting object. Bitfield DLCC is restricted to message objects configured in normal gateway mode. DLCC 11 Low rw User's Manual TwinCAN_X1, V2.1 22-76 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field FD Bits 13 Low Type rw Description FIFO Direction FD is only taken into account for a FIFO base object (the FD bits of all FIFO elements should have an identical value). It defines which transfer action (reception or transmission) leads to an update of the FIFO base object's CANPTR. 0 FIFO Reception: The CANPTR (of the FIFO base object) is updated after a correct reception of a data frame (DIR = `0') or a remote frame (DIR = `1') by the currently addressed message object. The CANPTR is left unchanged after any transmission. 1 FIFO Transmission: The CANPTR (of the FIFO base object) is updated after a correct transmission of a data frame (DIR = `1') or a remote frame (DIR = `0') from the currently addressed message object. The CANPTR is left unchanged after any reception. Bitfield FD is not correlated with bit DIR. Single Data Transfer Mode This bit is taken into account in any transfer mode (FIFO mode or as standard object, receive and transmit objects). 0 Control bit MSGVAL is not reset when this object has taken part in a successful data transfer (receive or transmit). 1 Control bit MSGVAL is automatically reset after a successful data transfer (receive or transmit) has taken place. Bit SDT is not taken into account for remote frames. Bit SDT has to be reset in all message objects belonging to a FIFO buffer. Single Transmission Try 0 Single transmission try is disabled. 1 Single transmission try is enabled. The corresponding TXRQ bit is reset immediately after the transmission has started1). SDT 14 Low rw STT 15 Low rw User's Manual TwinCAN_X1, V2.1 22-77 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field CANPTR Bits [4:0] High Type rwh Description CAN Pointer for FIFO/Gateway Functions Message object is configured in standard mode (MMC = `000'): No impact, CANPTR should be initialized with the respective message object number. Message object is configured as FIFO base object (MMC = `010'): CANPTR contains the number of the message object addressed by the associated CAN controller for the next transmit or receive operation. For initialization, CANPTR should be written with the message number of the respective FIFO base object. Message object is configured as FIFO slave object (MMC = `011'): CANPTR has to be initialized with the respective message object number of the FIFO base object. Message object is configured for normal gateway mode (MMC = `100'): CANPTR contains the number of the message object used as gateway destination object. Message object is configured as gateway destination object without FIFO functionality (MMC = `000'): If SRREN is set to `1', CANPTR has to be initialized with the number of the message object used as gateway source. The backward pointer is required to transfer remote frames from the destination to the source side. If SRREN is cleared, CANPTR is not evaluated and must be initialized with the respective message object number. Message object is configured for shared gateway mode (MMC = `101'): No impact, CANPTR has to be initialized with the respective message object number. For FIFO functionality (or gateway functionality with a FIFO as destination), CANPTRn should not be written by software while FIFO mode is activated and data transfer is in progress. This bitfield can be used to reset the FIFO by software. User's Manual TwinCAN_X1, V2.1 22-78 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field MMC Bits [10:8] High Type rw Description Message Object Mode Control Bitfield MMC controls the functionality of message object n. 000B Standard message object functionality 010B FIFO functionality enabled (base object) 011B FIFO functionality enabled (slave object) 100B Normal gateway functionality for incoming frames 101B Shared gateway functionality for incoming frames others reserved Reserved; returns `0' if read; should be written with `0'. 0 [7:5], r 12 Low [7:5], [15:11] High 1) As a result, a message will not be re-transmitted if it has lost arbitration or has been corrupted by an error frame. Note: Changes of bitfield CANPTR for transmission objects are only taken into account after setting bitfield MSGVAL to `10'. This avoids unintentional modification while the message object is still active by explicitly defining a timing instant for the update. Bitfield CANPTR for transmission objects can be written while MSGVAL is `01' or `10', the update always takes place by setting MSGVAL to `10'. Changes of bitfield CANPTR for receive objects are immediately taken into account. User's Manual TwinCAN_X1, V2.1 22-79 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.2.4 Global CAN Control/Status Registers The Receive Interrupt Pending Register indicates the pending receive interrupts for message object n. RXIPNDH Receive Interrupt Pending Register High RXIPNDL Receive Interrupt Pending Register Low 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 RXIPNDn (n = 31-16) rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXIPNDn (n = 15-0) rh Field RXIPNDn (n = 15-0) RXIPND (n = 31-16) Bits n Low n-16 High Type Description rh Message Object n Receive Interrupt Pending Bit RXIPNDn is set by hardware if message object n received a frame and bit RXIEn has been set. 0 No receive is pending for message object n. 1 Receive is pending for message object n. RXIPNDn can be cleared by software via resetting the corresponding bit INTPNDn. User's Manual TwinCAN_X1, V2.1 22-80 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Transmit Interrupt Pending Register indicates whether a transmit interrupt is pending for message object n. TXIPNDH Transmit Interrupt Pending Register High TXIPNDL Transmit Interrupt Pending Register Low 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 TXIPNDn (n = 31-16) rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXIPNDn (n = 15-0) rh Field TXIPNDn (n = 15-0) TXIPND (n = 31-16) Bits n Low n-16 High Type Description rh Message Object n Transmit Interrupt Pending Bit TXIPNDn is set by hardware if message object n transmitted a frame and bit TXIEn has been set. 0 No transmit is pending for message object n. 1 Transmit is pending for message object n. TXIPNDn can be cleared by software via resetting the corresponding bit INTPNDn. User's Manual TwinCAN_X1, V2.1 22-81 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.3 * * XC167 Module Implementation Details This section describes: the TwinCAN module related interfaces such as port connections and interrupt control all TwinCAN module related registers with its addresses and reset values 22.3.1 Interfaces of the TwinCAN Module In XC167 the TwinCAN module is connected to IO ports according to Figure 22-28. P4.4_rx fCAN MUX P4.5_rx P4.6_tx P4.7_tx Port 4 Control P4.4 P4.5 P4.6 RxDCA Address Decoder P4.7_rx TxDCA CAN0INT TwinCAN Module CAN1INT (Kernel) CAN2INT P7.4_rx P7.5_tx P7.6_rx TxDCB P7.7_tx ALTSEL P4.7 Port 7 Control P7.4 P7.5 P7.6 Interrupt Control CAN3INT CAN4INT CAN5INT CAN6INT CAN7INT ALTSEL MUX P7.7 RxDCB P9.0_rx P9.1_tx 3 PISEL 3 P9.2_rx P9.3_tx Port 9 Control P9.0 P9.1 P9.2 ALTSEL P9.3 MCA05498 Figure 22-28 TwinCAN Module IO Interface The input receive pins can be selected by bitfield RISA (for node A) and bitfield RISB (for node B) in the PISEL register. The output transmit pins are defined by the corresponding ALTSEL registers of Port 4, Port 7, or Port 9. The TwinCAN has eight interrupt request lines. Note: The interrupt node of interrupt request 7 of the TwinCAN can be shared with the SDLM module. User's Manual TwinCAN_X1, V2.1 22-82 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.3.2 TwinCAN Module Related External Registers Figure 22-29 shows the module related external registers which are required for programming the TwinCAN module. Port Registers Interrupt Registers System Registers ALTSEL0P4 DP4 ALTSEL0P7 DP7 ALTSEL0P9 DP9 CAN_0IC CAN_1IC CAN_2IC CAN_3IC CAN_4IC CAN_5IC CAN_6IC CAN_7IC CAN_PISEL MCA05499 Figure 22-29 TwinCAN Implementation Specific Registers User's Manual TwinCAN_X1, V2.1 22-83 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.3.2.1 System Registers Register CAN_PISEL allows the user to select the input pins for the two TwinCAN receive signals RXDCA and RXDCB. CAN_PISEL TwinCAN Port Input Select Register 15 14 13 12 11 0 r 10 9 8 7 6 5 4 RISB rw Reset Value: 0000H 3 2 1 RISA rw 0 Field RISA Bits [2:0] Type Description rw Receive Input Selection for Node A Bitfield RISA defines the input pin for the TwinCAN receive line RXDCA for node A. 000 The input pin for RXDCA is P4.5 001 The input pin for RXDCA is P4.7 010 The input pin for RXDCA is P7.6 011 The input pin for RXDCA is P9.2 1XX Reserved. Receive Input Selection for Node B Bitfield RISB defines the input pin for the TwinCAN receive line RXDCB for node B. 000 The input pin for RXDCB is P4.4 001 The input pin for RXDCB is P9.0 010 The input pin for RXDCB is P7.4 011 Reserved. 1XX Reserved. Reserved; returns `0' if read; should be written with `0'. RISB [5:3] rw 0 [15:6] r User's Manual TwinCAN_X1, V2.1 22-84 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.3.2.2 Port Registers The port registers required to program to TwinCAN operation are listed as follows. ALTSEL0P4 P4 Alternate Select Register 0 15 14 13 12 0 r 11 10 9 8 7 P7 rw 6 P6 rw 5 4 Reset Value: 0000H 3 0 r 2 1 0 Field ALTSEL0 P4.y Bits 6, 7 Type rw Description P4 Alternate Select Register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function DP4 P4 Direction Ctrl. Register 15 14 13 12 0 r 11 10 9 8 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw Reset Value: 0000H 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw Field DP4.y Bits 7...4 Type rw Description Port Direction Register DP4 Bit y 0 Port line P4.y is an input (high-impedance) 1 Port line P4.y is an output User's Manual TwinCAN_X1, V2.1 22-85 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module ALTSEL0P7 P7 Alternate Select Register 0 15 14 13 12 0 r 11 10 9 8 7 P7 rw 6 0 rw 5 P5 rw 4 0 rw Reset Value: 0000H 3 2 0 r 1 0 Field ALTSEL0 P7.y Bits 7, 5 Type rw Description P7 Alternate Select Register 0 Bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function DP7 P7 Direction Ctrl. Register 15 14 13 12 0 r 11 10 9 8 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw Reset Value: 0000H 3 2 0 r 1 0 Field DP7.y Bits 7...4 Type rw Description Port Direction Register DP7 Bit y 0 Port line P7.y is an input (high-impedance) 1 Port line P7.y is an output Note: Shaded bits are not related to TwinCAN operation. User's Manual TwinCAN_X1, V2.1 22-86 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module ALTSEL0P9 P9 Alternate Select Register 0 15 14 13 12 11 0 r 10 9 8 7 6 5 0 rw 4 0 rw Reset Value: 0000H 3 P3 rw 2 0 rw 1 P1 rw 0 0 rw Field ALTSEL0 P9.y Bits 3, 1 Type rw Description P9 Alternate Select Register 0 Bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function ALTSEL1P9 P9 Alternate Select Register 1 15 14 13 12 11 0 r 10 9 8 7 6 5 0 rw 4 0 rw Reset Value: 0000H 3 P3 rw 2 0 rw 1 P1 rw 0 0 rw Field ALTSEL1 P9.y Bits 3, 1 Type rw Description P9 Alternate Select Register 1 Bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function User's Manual TwinCAN_X1, V2.1 22-87 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module DP9 P9 Direction Ctrl. Register 15 14 13 12 11 0 r 10 9 8 7 6 5 P5 rw 4 P4 rw Reset Value: 0000H 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw Field DP9.y Bits 3...0 Type rw Description Port Direction Register DP9 Bit y 0 Port line P9.y is an input (high-impedance) 1 Port line P9.y is an output Note: Shaded bits are not related to TwinCAN operation. User's Manual TwinCAN_X1, V2.1 22-88 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Table 22-9 shows the required register setting to configure the IO lines of the TwinCAN module for operation. Table 22-9 Port Lines TwinCAN IO Selection and Setup Alternate Select Register Port Input Select Register Direction Control Register DP4.P5 = 0 DP4.P6 = 1 DP4.P7 = 0 DP7.P6 = 0 DP7.P7 = 1 DP9.P2 = 0 DP9.P3 = 1 IO TwinCAN Node A P4.5 / RxDCA P4.6 / TxDCA P4.7 / RxDCA P7.6 / RxDCA P7.7 / TxDCA P9.2 / RxDCA P9.3 / TxDCA - ALTSEL0P4.P6 = 1 - - ALTSEL0P7.P7 = 1 - ALTSEL0P9.P3 = 1 and ALTSEL1P9.P3 =1 - ALTSEL0P4.P7 = 1 - ALTSEL0P7.P5 = 1 - ALTSEL0P9.P1 = 1 and ALTSEL1P9.P1 =1 CAN_PISEL[2:0] = 000 - CAN_PISEL[2:0] = 001 CAN_PISEL[2:0] = 010 - CAN_PISEL[2:0] = 011 - Input Output Input Input Output Input Output TwinCAN Node B P4.4 / RxDCB P4.7 / TxDCB P7.4 / RxDCB P7.5 / TxDCB P9.0 / RxDCB P9.1 / TxDCB CAN_PISEL[5:3] = 000 - CAN_PISEL[5:3] = 010 - CAN_PISEL[5:3] = 001 - DP4.P4 = 0 DP4.P7 = 1 DP7.P4 = 0 DP7.P5 = 1 DP9.P0 = 0 DP9.P1 = 1 Input Output Input Output Input Output Note: The ALTSEL1 registers of Port 7 and Port 4 are `don't care' for selecting the TwinCAN alternate output function. User's Manual TwinCAN_X1, V2.1 22-89 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.3.2.3 Interrupt Registers The interrupts of the TwinCAN module are controlled by the following interrupt control registers: * * * * * * * * CAN_0IC CAN_1IC CAN_2I CAN_3I CAN_4I CAN_5IC CAN_6IC CAN_7IC All interrupt control registers have the same structure. Refer to the System Units for its description and also details on interrupt handling and processing. User's Manual TwinCAN_X1, V2.1 22-90 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 22.3.3 Register Table Table 22-10 shows the system registers related to the TwinCAN module. It summarizes the addresses and reset values. In order to simplify the kernel description, the prefix `CAN_' is added only in this register list. The start address for the TwinCAN module is 20'0000H, the register offsets (relative to this address) are given in the TwinCAN kernel description. See Figure 22-27. A full register listing of all CAN registers is provided in register table section and in the system book. Table 22-10 TwinCAN Module Register Summary Name Description Address1) 16-Bit TwinCAN Module System Registers CAN_PISEL CAN_0IC CAN_1IC CAN_2IC CAN_3IC CAN_4IC CAN_5IC CAN_6IC CAN_7IC2) TwinCAN Port Input Select Register TwinCAN Interrupt Control Register for the CAN interrupt node 0. TwinCAN Interrupt Control Register for the CAN interrupt node 1. TwinCAN Interrupt Control Register for the CAN interrupt node 2. TwinCAN Interrupt Control Register for the CAN interrupt node 3. TwinCAN Interrupt Control Register for the CAN interrupt node 4. TwinCAN Interrupt Control Register for the CAN interrupt node 5. TwinCAN Interrupt Control Register for the CAN interrupt node 6. TwinCAN Interrupt Control Register for the CAN interrupt node 7. 20'0004H F196H F142H F144H F146H F148H F14AH F14CH F14EH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Reset Value 1) The 8-bit short addresses are not available for the TwinCAN module kernel registers. 2) In the XC167 device, the CAN interrupt node 7 is shared with the SDLM interrupt 1. In order to avoid mismatches if the CAN interrupt 7 is used by the TwinCAN module, the SDLM interrupt 1 should be mapped to a common SDLM interrupt 0 (see register SDLM_PISEL). User's Manual TwinCAN_X1, V2.1 22-91 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set 23 Register Set This chapter summarizes all the kernel and module related external registers of the peripherals. The register list is organized into two parts - the first for PD+BUS peripherals and the second for LXBUS peripherals. 23.1 PD+BUS Peripherals Note: The address space for PD+BUS peripherals is assigned to Segment 0. Table 23-1 Short Name PD+BUS Register Listing Address Physical 8-bit ASC0_CON ASC0_TBUF ASC0_RBUF ASC0_ ABCON ASC0_ ABSTAT ASC0_BG ASC0_FDV ASC0_PMW ASC0_ RXFCON ASC0_ TXFCON FFB0H FEB0H FEB2H F1B8H F0B8H FEB4H FEB6H FEAAH F0C6H F0C4H D8H 58H 59H DCH 5CH 5AH 5BH 55H 63H 62H 5DH DCH 5CH 5DH DEH Area SFR SFR SFR ASC0 Control Register ASC0 Transmit Buffer Register ASC0 Receive Buffer Register Description Reset Value Asynchronous/Synchronous Serial Interface 0 (ASC0) 0000H 0000H 0000H 0000H 0000H 0000H 0000H ESFR ASC0 Autobaud Control Register ESFR ASC0 Autobaud Status Register SFR SFR SFR ASC0 Baud Rate Generator Reload Register ASC0 Fractional Divider Register ASC0 IrDA Pulse Mode and Width 0000H Reg. 0000H 0000H 0000H 0000H 0000H 0000H 0000H ESFR ASC0 Receive FIFO Control Register ESFR ASC0 Transmit FIFO Control Register ESFR ASC0 FIFO Status Register SFR SFR SFR ASC1 Control Register ASC1 Transmit Buffer Register ASC1 Receive Buffer Register ASC0_FSTAT F0BAH ASC1_CON ASC1_TBUF ASC1_RBUF ASC1_ ABCON FFB8H FEB8H FEBAH F1BCH Asynchronous/Synchronous Serial Interface 1 (ASC1) ESFR ASC1 Autobaud Control Register User's Manual RegSet_X71, V2.0 23-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name ASC1_ ABSTAT ASC1_BG ASC1_FDV ASC1_PMW ASC1_ RXFCON ASC1_ TXFCON F0BCH FEBCH FEBEH FEACH F0A6H F0A4H PD+BUS Register Listing (cont'd) Address Physical 8-bit 5EH 5EH 5FH 56H 53H 52H 5FH D9H 5AH 58H 59H AFH 2FH 2DH 2EH A0H A1H A2H Area ESFR ASC1 Autobaud Status Register SFR SFR SFR ASC1 Baud Rate Generator Reload Register ASC1 Fractional Divider Register Description Reset Value 0000H 0000H 0000H ASC1 IrDA Pulse Mode and Width 0000H Reg. 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H ESFR ASC1 Receive FIFO Control Register ESFR ASC1 Transmit FIFO Control Register ESFR ASC1 FIFO Status Register SFR SSC0 Control Register ASC1_FSTAT F0BEH SSC0_CON SSC0_BR SSC0_TB SSC0_RB SSC1_CON SSC1_BR SSC1_TB SSC1_RB GPT12E_ T2CON GPT12E_ T3CON GPT12E_ T4CON FFB2H F0B4H F0B0H F0B2H FF5EH F05EH F05AH F05CH FF40H FF42H FF44H Synchronous Serial Channel 0 (SSC0) ESFR SSC0 Baudrate Timer Reload Register ESFR SSC0 Transmit Buffer Reg. ESFR SSC0 Receive Buffer Reg. SFR SSC1 Control Register Synchronous Serial Channel 1 (SSC1) ESFR SSC1 Baudrate Timer Reload Register ESFR SSC1 Transmit Buffer Reg. ESFR SSC1 Receive Buffer Reg. SFR SFR SFR GPT12E Timer 2 Control Register GPT12E Timer 3 Control Register GPT12E Timer 4 Control Register General Purpose Timer Unit (GPT12E) User's Manual RegSet_X71, V2.0 23-2 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name GPT12E_ T5CON GPT12E_ T6CON GPT12E_ CAPREL GPT12E_T2 GPT12E_T3 GPT12E_T4 GPT12E_T5 GPT12E_T6 RTC_CON RTC_T14 RTC_RTCL RTC_RTCH RTC_RELL RTC_RELH RTC_ISNC CC1_M0 CC1_M1 CC1_M2 CC1_M3 CC1_SEE FF46H FF48H FE4AH FE40H FE42H FE44H FE46H FE48H F110H F0D2H F0D4H F0D6H F0CCH F0CEH F10CH FF52H FF54H FF56H FF58H FE2EH PD+BUS Register Listing (cont'd) Address Physical 8-bit A3H A4H 25H 20H 21H 22H 23H 24H 88H 69H 68H 6AH 6BH 66H 67H 86H A9H AAH ABH ACH 17H Area SFR SFR SFR SFR SFR SFR SFR SFR GPT12E Timer 5 Control Register GPT12E Timer 6 Control Register Description Reset Value 0000H 0000H GPT12E Capture/Reload Register 0000H GPT12E Timer 2 Register GPT12E Timer 3 Register GPT12E Timer 4 Register GPT12E Timer 5 Register GPT12E Timer 6 Register 0000H 0000H 0000H 0000H 0000H 8003H UUUUH UUUUH UUUUH UUUUH 0000H 0000H 0000H Real Time Clock (RTC) ESFR RTC Control Register, low word ESFR Timer 14 Register ESFR Timer 14 Reload Register ESFR RTC Timer Low Register ESFR RTC Timer High Register ESFR RTC Reload Low Register ESFR RTC Reload High Register ESFR RTC Interrupt Subnode Register SFR SFR SFR SFR SFR RTC_T14REL F0D0H Capture/Compare Unit 1 (CAPCOM1) CAPCOM 1 Mode Control Register 0000H 0 CAPCOM 1 Mode Control Register 0000H 1 CAPCOM 1 Mode Control Register 0000H 2 CAPCOM 1 Mode Control Register 0000H 3 CAPCOM1 Single Event Enable Register 0000H User's Manual RegSet_X71, V2.0 23-3 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name CC1_SEM CC1_DRM CC1_OUT CC1_T0 CC1_T0REL CC1_T1 CC1_T1REL FE2CH FF5AH FF5CH FE50H FE54H FE52H FE56H PD+BUS Register Listing (cont'd) Address Physical 8-bit 16H ADH AEH 28H 2AH 29H 2BH A8H 31H 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH Area SFR SFR SFR SFR SFR SFR SFR SFR CAPCOM1 Single Event Mode Register Description Reset Value 0000H CAPCOM1 Double Register Mode 0000H Register CAPCOM1 Output Register CAPCOM 1 Timer 0 Register CAPCOM 1 Timer 0 Reload Register CAPCOM 1 Timer 1 Register CAPCOM 1 Timer 1 Reload Register CAPCOM 1 Timer 0 and Timer 1 Control Register CAPCOM 1 Register 0 CAPCOM 1 Register 1 CAPCOM 1 Register 2 CAPCOM 1 Register 3 CAPCOM 1 Register 4 CAPCOM 1 Register 5 CAPCOM 1 Register 6 CAPCOM 1 Register 7 CAPCOM 1 Register 8 CAPCOM 1 Register 9 CAPCOM 1 Register 10 CAPCOM 1 Register 11 CAPCOM 1 Register 12 CAPCOM 1 Register 13 CAPCOM 1 Register 14 CAPCOM 1 Register 15 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H CC1_T01CON FF50H CC1_IOC CC1_CC0 CC1_CC1 CC1_CC2 CC1_CC3 CC1_CC4 CC1_CC5 CC1_CC6 CC1_CC7 CC1_CC8 CC1_CC9 CC1_CC10 CC1_CC11 CC1_CC12 CC1_CC13 CC1_CC14 CC1_CC15 F062H FE80H FE82H FE84H FE86H FE88H FE8AH FE8CH FE8EH FE90H FE92H FE94H FE96H FE98H FE9AH FE9CH FE9EH ESFR CAPCOM 1 I/O Control Register SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR User's Manual RegSet_X71, V2.0 23-4 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name PD+BUS Register Listing (cont'd) Address Physical 8-bit CC2_M4 CC2_M5 CC2_M6 CC2_M7 CC2_SEE CC2_SEM CC2_DRM CC2_OUT CC2_T7 CC2_T8 CC2_T7REL CC2_T8REL FF22H FF24H FF26H FF28H FE2AH FE28H FF2AH FF2CH F050H F052H F054H F056H 91H 92H 93H 94H 15H 14H 95H 96H 28H 29H 2AH 2BH 90H 33H 30H 31H 32H 33H 34H 35H 36H Area SFR SFR SFR SFR SFR SFR SFR SFR Description Reset Value Capture / Compare Unit 2 (CAPCOM2) CAPCOM2 Mode Control Register 0000H 4 CAPCOM2 Mode Control Register 0000H 5 CAPCOM2 Mode Control Register 0000H 6 CAPCOM2 Mode Control Register 0000H 7 CAPCOM2 Single Event Enable Register CAPCOM2 Single Event Mode Register 0000H 0000H CAPCOM2 Double Register Mode 0000H Register CAPCOM2 Output Register 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H V2.0, 2004-04 ESFR CAPCOM 2 Timer 7 Register ESFR CAPCOM 2 Timer 8 Register ESFR CAPCOM 2 Timer 7 Reload Register ESFR CAPCOM 2 Timer 8 Reload Register SFR CAPCOM 2 Timer 7 and Timer 8 Control Register CAPCOM 2 Register 16 CAPCOM 2 Register 17 CAPCOM 2 Register 18 CAPCOM 2 Register 19 CAPCOM 2 Register 20 CAPCOM 2 Register 21 CAPCOM 2 Register 22 23-5 CC2_T78CON FF20H CC2_IOC CC2_CC16 CC2_CC17 CC2_CC18 CC2_CC19 CC2_CC20 CC2_CC21 CC2_CC22 F066H FE60H FE62H FE64H FE66H FE68H FE6AH FE6CH ESFR CAPCOM 2 I/O Control Register SFR SFR SFR SFR SFR SFR SFR User's Manual RegSet_X71, V2.0 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name CC2_CC23 CC2_CC24 CC2_CC25 CC2_CC26 CC2_CC27 CC2_CC28 CC2_CC29 CC2_CC30 CC2_CC31 CCU6_T12 CCU6_ T12DTC FE6EH FE70H FE72H FE74H FE76H FE78H FE7AH FE7CH FE7EH E890H E894H PD+BUS Register Listing (cont'd) Address Physical 8-bit 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH - - - - - - - - - - - - - - Area SFR SFR SFR SFR SFR SFR SFR SFR SFR IO IO IO IO IO IO IO IO IO IO IO IO IO IO CAPCOM 2 Register 23 CAPCOM 2 Register 24 CAPCOM 2 Register 25 CAPCOM 2 Register 26 CAPCOM 2 Register 27 CAPCOM 2 Register 28 CAPCOM 2 Register 29 CAPCOM 2 Register 30 CAPCOM 2 Register 31 Timer 12 Counter Register Timer 12 Period Register Dead-Time Control Register for Timer 12 Description Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Capture / Compare Unit 6 (CCU6) CCU6_T12PR E892H CCU6_CC60R E898H CCU6_CC61R E89AH CCU6_CC62R E89CH CCU6_ CC60SR CCU6_ CC61SR CCU6_ CC62SR CCU6_T13 E8A0H E8A2H E8A4H E8B0H Capture/Compare Register (Ch. 0) 0000H Capture/Compare Register (Ch. 1) 0000H Capture/Compare Register (Ch. 2) 0000H Capture/Compare Shadow Register (Ch. 0) Capture/Compare Shadow Register (Ch. 1) Capture/Compare Shadow Register (Ch. 2) Timer 13 Counter Register Timer 13 Period Register Compare Register for Timer 13 Compare Shadow Register for Timer 13 Compare State Register 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H CCU6_T13PR E8B2H CCU6_CC63R E8B4H CCU6_ CC63SR CCU6_ CMPSTAT E8B6H E8A8H User's Manual RegSet_X71, V2.0 23-6 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name CCU6_ CMPMODIF E8AAH PD+BUS Register Listing (cont'd) Address Physical 8-bit - - - - - - - - - - - - - - - - Area IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Compare State Modification Register Timer Control Register 0 Timer Control Register 2 Timer Control Register 4 Modulation Control Register Trap Control Register Passive State Level Register T12 Capture/Compare Mode Select Register Multi-Channel Mode Output Shadow Register Multi-Channel Mode Output Register Multi-Channel Mode Control Register Description Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H CCU6_TCTR0 E8ACH CCU6_TCTR2 E8AEH CCU6_TCTR4 E8A6H CCU6_ MODCTR CCU6_ TRPCTR CCU6_PSLR CCU6_ T12MSEL CCU6_ MCMOUTS CCU6_ MCMOUT CCU6_ MCMCTR CCU6_IS CCU6_ISS CCU6_ISR CCU6_INP CCU6_IEN E8C0H E8C2H E8C4H E8C6H E8CAH E8CCH E8CEH E8D0H E8D2H E8D4H E8D6H E8D8H Capture/Compare Interrupt Status 0000H Register Capture/Compare Interrupt Status 0000H Set Register Capture/Compare Interrupt Status 0000H Reset Register Capture/Compare Interrupt Node Pointer Register Capture/Compare Interrupt Node Pointer Register A/D Converter Control Register A/D Converter Control Register A/D Converter Control Register 0 3940H 0000H A/D Converter (ADC) ADC_CON ADC_CON1 ADC_CTR0 FFA0H FFA6H FFBEH D0H D3H DFH SFR SFR SFR 0000H 0000H 1000H User's Manual RegSet_X71, V2.0 23-7 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name ADC_CTR2 F09CH PD+BUS Register Listing (cont'd) Address Physical 8-bit 4EH 4FH 50H 50H - - - - - - ADC_CTR2IN F09EH ADC_DAT ADC_DAT2 IIC Module IIC_ST IIC_CON IIC_CFG IIC_ADR IIC_RTBL IIC_RTBH E604H E602H E600H E606H E608H E60AH IO IO IO IO IO IO IIC Status Register IIC Control Register IIC Configuration Register IIC Address Register IIC Receive/Transmit Buffer Low Register IIC Receive/Transmit Buffer High Register 0000H 0000H 0000H 0000H 0000H 0000H FEA0H F0A0H Area ESFR A/D Converter Control Register 2 ESFR A/D Converter Injection Control Register 2 SFR A/D Converter Result Register ESFR A/D Converter 2 Result Register Description Reset Value 0000H 0000H 0000H 0000H User's Manual RegSet_X71, V2.0 23-8 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name Interrupt Control SSC0_TIC SSC0_RIC SSC0_EIC SSC1_TIC SSC1_RIC SSC1_EIC ASC0_TIC ASC0_RIC ASC0_EIC ASC0_TBIC ASC0_ABIC ASC1_TIC ASC1_RIC ASC1_EIC ASC1_TBIC ASC1_ABIC FF72H FF74H FF76H F1AAH F1ACH F1AEH FF6CH FF6EH FF70H F19CH F15CH F182H F18AH F192H F150H F1BAH B9H BAH BBH D5H D6H D7H B6H B7H B8H CEH AEH C1H C5H C9H A8H DDH SFR SFR SFR SSC0 Transmit Interrupt Control Register SSC0 Receive Interrupt Control Register SSC0 Error Interrupt Control Register 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H PD+BUS Register Listing (cont'd) Address Physical 8-bit Area Description Reset Value ESFR SSC1 Transmit Interrupt Control Register SFR SSC1 Receive Interrupt Control Register ESFR SSC1 Error Interrupt Control Register SFR SFR SFR ASC0 Transmit Interrupt Control Register ASC0 Receive Interrupt Control Register ASC0 Error Interrupt Control Register ESFR ASC0 Transmit Buffer Interrupt Control Register ESFR ASC0 Autobaud Interrupt Control Register ESFR ASC1 Transmit Interrupt Control Register ESFR ASC1 Receive Interrupt Control Register ESFR ASC1 Error Interrupt Control Register ESFR ASC1 Transmit Buffer Interrupt Control Register ESFR ASC1 Autobaud Interrupt Control Register User's Manual RegSet_X71, V2.0 23-9 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name GPT12E_ T2IC GPT12E_ T3IC GPT12E_ T4IC GPT12E_ T5IC GPT12E_ T6IC GPT12E_ CRIC CC1_T0IC CC1_T1IC CC2_T7IC CC2_T8IC CC1_CC0IC CC1_CC1IC CC1_CC2IC CC1_CC3IC CC1_CC4IC CC1_CC5IC FF60H FF62H FF64H FF66H FF68H FF6AH FF9CH FF9EH F17AH F17CH FF78H FF7AH FF7CH FF7EH FF80H FF82H PD+BUS Register Listing (cont'd) Address Physical 8-bit B0H B1H B2H B3H B4H B5H CEH CFH BDH BEH BCH BDH BEH BFH C0H C1H Area SFR SFR SFR SFR SFR SFR SFR SFR Description Reset Value GPT12E Timer 2 Interrupt Control 0000H Register GPT12E Timer 3 Interrupt Control 0000H Register GPT12E Timer 4 Interrupt Control 0000H Register GPT12E Timer 5 Interrupt Control 0000H Register GPT12E Timer 6 Interrupt Control 0000H Register GPT12E CAPREL Interrupt Control Register 0000H CAPCOM Timer 0 Interrupt Control 0000H Register CAPCOM Timer 1 Interrupt Control 0000H Register ESFR CAPCOM Timer 7 Interrupt Control 0000H Register ESFR CAPCOM Timer 8 Interrupt Control 0000H Register SFR SFR SFR SFR SFR SFR CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 Interrupt Control Register CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 Interrupt Control Register 0000H 0000H 0000H 0000H 0000H 0000H User's Manual RegSet_X71, V2.0 23-10 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name CC1_CC6IC CC1_CC7IC CC1_CC8IC CC1_CC9IC CC1_CC10IC CC1_CC11IC CC1_CC12IC CC1_CC13IC CC1_CC14IC CC1_CC15IC CC2_CC16IC CC2_CC17IC CC2_CC18IC CC2_CC19IC CC2_CC20IC CC2_CC21IC FF84H FF86H FF88H FF8AH FF8CH FF8EH FF90H FF92H FF94H FF96H F160H F162H F164H F166H F168H F16AH PD+BUS Register Listing (cont'd) Address Physical 8-bit C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH B0H B1H B2H B3H B4H B5H Area SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR CAPCOM Register 6 Interrupt Control Register CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 Interrupt Control Register Description Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H ESFR CAPCOM Register 16 Interrupt Control Register ESFR CAPCOM Register 17 Interrupt Control Register ESFR CAPCOM Register 18 Interrupt Control Register ESFR CAPCOM Register 19 Interrupt Control Register ESFR CAPCOM Register 20 Interrupt Control Register ESFR CAPCOM Register 21 Interrupt Control Register User's Manual RegSet_X71, V2.0 23-11 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name CC2_CC22IC CC2_CC23IC CC2_CC24IC CC2_CC25IC CC2_CC26IC CC2_CC27IC CC2_CC28IC CC2_CC29IC CC2_CC30IC CC2_CC31IC CCU6_IC CCU6_EIC F16CH F16EH F170H F172H F174H F176H F178H F184H F18CH F194H F140H F188H PD+BUS Register Listing (cont'd) Address Physical 8-bit B6H B7H B8H B9H BAH BBH BCH C2H C6H CAH A0H C4H Area ESFR CAPCOM Register 22 Interrupt Control Register ESFR CAPCOM Register 23 Interrupt Control Register ESFR CAPCOM Register 24 Interrupt Control Register ESFR CAPCOM Register 25 Interrupt Control Register ESFR CAPCOM Register 26 Interrupt Control Register ESFR CAPCOM Register 27 Interrupt Control Register ESFR CAPCOM Register 28 Interrupt Control Register ESFR CAPCOM Register 29 Interrupt Control Register ESFR CAPCOM Register 30 Interrupt Control Register ESFR CAPCOM Register 31 Interrupt Control Register Description Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H ESFR Interrupt Control Register for other 0000H Interrupts (module intr. node I3) ESFR Interrupt Control Register for Emergency Interrupts (module intr. node I2) ESFR Interrupt Control Register for T12 Interrupts (module intr. node I0) ESFR Interrupt Control Register for T13 Interrupts (module intr. node I1) SFR SFR A/D Converter End of Conversion Interrupt Control Register A/D Converter Overrun Error Interrupt Control Register 0000H CCU6_T12IC CCU6_T13IC ADC_CIC ADC_EIC F190H F198H FF98H FF9AH C8H CCH CCH CDH 0000H 0000H 0000H 0000H User's Manual RegSet_X71, V2.0 23-12 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name IIC_DIC IIC_PEIC CAN_0IC CAN_1IC CAN_2IC CAN_3IC CAN_4IC CAN_5IC CAN_6IC CAN_7IC EOPIC PLL_IC RTC_IC Ports PICON POCON0L POCON0H POCON1L POCON1H POCON2 F1C4H F080H F082H F084H F086H F088H E2H 40H 41H 42H 43H 44H ESFR Port Input Threshold Control Register ESFR P0L Output Control Register ESFR P0H Output Control Register ESFR P1L Output Control Register ESFR P1H Output Control Register ESFR P2 Output Control Register 0000H 0000H 0000H 0000H 0000H 0000H F186H F18EH F196H F142H F144H F146H F148H F14AH F14CH F14EH F180H F19EH F1A0H PD+BUS Register Listing (cont'd) Address Physical 8-bit C3H C7H CBH A1H A2H A3H A4H A5H A6H A7H C0H CFH D0H Area ESFR IIC Data Transfer Event Interrupt Control Register ESFR IIC Protocol Event Interrupt Control Register ESFR TwinCAN Interrupt Control Register 0 ESFR TwinCAN Interrupt Control Register 1 ESFR TwinCAN Interrupt Control Register 2 ESFR TwinCAN Interrupt Control Register 3 ESFR TwinCAN Interrupt Control Register 4 ESFR TwinCAN Interrupt Control Register 5 ESFR TwinCAN Interrupt Control Register 6 ESFR TwinCAN Interrupt Control Register 7 ESFR End of PEC Subchannel Interrupt Control Register ESFR PLL Interrupt Control Register ESFR RTC Interrupt Control Register Description Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H User's Manual RegSet_X71, V2.0 23-13 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name POCON3 POCON4 POCON6 POCON7 POCON9 POCON20 P0L P0H DP0L DP0H P1L P1H DP1L DP1H ALTSEL0P1L P2 DP2 ODP2 ALTSEL0P2 P3 DP3 ODP3 ALTSEL0P3 ALTSEL1P3 P4 DP4 ODP4 ALTSEL0P4 F08AH F08CH F08EH F090H F094H F0AAH FF00H FF02H F100H F102H FF04H FF06H F104H F106H F130H FFC0H FFC2H F1C2H F122H FFC4H FFC6H F1C6H F126H F128H FFC8H FFCAH F1CAH F12AH PD+BUS Register Listing (cont'd) Address Physical 8-bit 45H 46H 47H 48H 4AH 55H 80H 81H 80H 81H 82H 83H 82H 83H 98H 90H E0H E1H E1H 91H E2H E3H E3H 93H 94H E4H E5H E5H 95H Area ESFR P3 Output Control Register ESFR P4 Output Control Register ESFR P6 Output Control Register ESFR P7 Output Control Register ESFR P9 Output Control Register ESFR P20 Output Control Register SFR SFR PORT0 Low Register PORT0 High Register Description Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H ESFR P0L Direction Control Register ESFR P0H Direction Control Register SFR SFR PORT1 Low Register PORT1 High Register ESFR P1L Direction Control Register ESFR P1H Direction Control Register ESFR P1L Alternate Select Register 0 ESFR P1H Alternate Select Register 0 SFR SFR Port 2 Data Register P2 Direction Control Register ALTSEL0P1H F120H ESFR P2 Open Drain Control Register ESFR P2 Alternate Select Register 0 SFR SFR Port 3 Data Register P3 Direction Control Register ESFR P3 Open Drain Control Register ESFR P3 Alternate Select Register 0 ESFR P3 Alternate Select Register 1 SFR SFR Port 4 Data Register P4 Direction Control Register ESFR P4 Open Drain Control Register ESFR P4 Alternate Select Register 0 User's Manual RegSet_X71, V2.0 23-14 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 Short Name ALTSEL1P4 P5 P5DIDIS P6 DP6 ODP6 ALTSEL0P6 P7 DP7 ODP7 ALTSEL0P7 ALTSEL1P7 P9 DP9 ODP9 ALTSEL0P9 ALTSEL1P9 P20 DP20 F136H FFA2H FFA4H FFCCH FFCEH F1CEH F12CH FFD0H FFD2H F1D2H F13CH F13EH FF16H FF18H FF1AH F138H F13AH FFB4H FFB6H PD+BUS Register Listing (cont'd) Address Physical 8-bit 9BH D1H D2H E6H E7H E7H 96H E8H E9H E9H 9EH 9FH 8BH 8CH 8DH 9CH 9DH DAH DBH Area ESFR P4 Alternate Select Register 1 SFR SFR SFR SFR Port 5 Data Register Port 5 Digital Input Disable Register Port 6 Data Register P6 Direction Control Register Description Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H ESFR P6 Open Drain Control Register ESFR P6 Alternate Select Register 0 SFR SFR Port 7 Data Register P7 Direction Control Register ESFR P7 Open Drain Control Register ESFR P7 Alternate Select Register 0 ESFR P7 Alternate Select Register 1 SFR SFR SFR Port 9 Data Register P9 Direction Control Register P9 Open Drain Control Register ESFR P9 Alternate Select Register 0 ESFR P9 Alternate Select Register 1 SFR SFR Port 20 Data Register P20 Direction Control Register User's Manual RegSet_X71, V2.0 23-15 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set 23.2 LXBUS Peripherals Note: The address space for LXBUS peripherals is assigned to Segment 32; it may be changed by user SW. Table 23-2 Short Name TwinCAN CAN_PISEL CAN_ACR CAN_ASR CAN_AIR CAN_ABTRL CAN_ABTRH CAN_AGINP CAN_AFCRL CAN_AFCRH CAN_AIMRL0 CAN_AIMRH0 CAN_AIMR4 CAN_AECNTL CAN_AECNTH CAN_BCR CAN_BSR CAN_BIR CAN_BBTRL CAN_BBTRH CAN_BGINP CAN_BFCRL CAN_BFCRH CAN_BIMRL0 CAN_BIMRH0 CAN_BIMR4 20'0004H 20'0200H 20'0204H 20'0208H 20'020CH 20'020EH 20'0210H 20'0214H 20'0216H 20'0218H 20'021AH 20'021CH 20'0220H 20'0222H 20'0240H 20'0244H 20'0248H 20'024CH 20'024EH 20'0250H 20'0254H 20'0256H 20'0258H 20'025AH 20'025CH TwinCAN Port Input Select Register Node A Control Register Node A Status Register Node A Interrupt Pending Register Node A Bit Timing Register Low Node A Bit Timing Register High Node A Frame Counter Register Low Node A Frame Counter Register High Node A INTID Mask Register 0 Low Node A INTID Mask Register 0 High Node A INTID Mask Register 4 Node A Error Counter Register Low Node A Error Counter Register High Node B Control Register Node B Status Register Node B Interrupt Pending Register Node B Bit Timing Register Low Node B Bit Timing Register High Node B Frame Counter Register Low Node B Frame Counter Register High Node B INTID Mask Register 0 Low Node B INTID Mask Register 0 High Node B INTID Mask Register 4 0000H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0060H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H V2.0, 2004-04 LXBUS Register Listing Physical Address Description Reset Value Node A Global Int. Node Pointer Register 0000H Node B Global Int. Node Pointer Register 0000H User's Manual RegSet_X71, V2.0 23-16 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-2 Short Name CAN_BECNTL CAN_BECNTH CAN_RXIPNDL CAN_RXIPNDH CAN_TXIPNDL CAN_TXIPNDH Interrupt Control CAN_0IC CAN_1IC CAN_2IC CAN_3IC CAN_4IC CAN_5IC CAN_6IC CAN_7IC 00'F196H1) 00'F142H1) 00'F144H1) 00'F146H1) 00'F148H1) 00'F14AH1) 00'F14CH1) 00'F14EH1) TwinCAN Interrupt Control Register 0 TwinCAN Interrupt Control Register 1 TwinCAN Interrupt Control Register 2 TwinCAN Interrupt Control Register 3 TwinCAN Interrupt Control Register 4 TwinCAN Interrupt Control Register 5 TwinCAN Interrupt Control Register 6 TwinCAN Interrupt Control Register 7 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H LXBUS Register Listing (cont'd) Physical Address 20'0260H 20'0262H 20'0284H 20'0286H 20'0288H 20'028AH Description Node B Error Counter Register Low Node B Error Counter Register High Receive Interrupt Pending Register Low Receive Interrupt Pending Register High Transmit Interrupt Pending Register Low Transmit Interrupt Pending Register High Reset Value 0000H 0060H 0000H 0000H 0000H 0000H 1) This register is located in the ESFR area. The base address of each Message Object n, where n = 0-31, is listed in Table 23-3. The offset address of each register in Message Object n is given in Table 23-4. Table 23-3 Base Address of Message Objects Base Address 20'0300H 20'0320H 20'0340H 20'0360H 20'0380H 20'03A0H 20'03C0H 20'03E0H 20'0400H 23-17 V2.0, 2004-04 Message Object Number Message Object 0 Message Object 1 Message Object 2 Message Object 3 Message Object 4 Message Object 5 Message Object 6 Message Object 7 Message Object 8 User's Manual RegSet_X71, V2.0 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-3 Base Address of Message Objects (cont'd) Base Address 20'0420H 20'0440H 20'0460H 20'0480H 20'04A0H 20'04C0H 20'04E0H 20'0500H 20'0520H 20'0540H 20'0560H 20'0580H 20'05A0H 20'05C0H 20'05E0H 20'0600H 20'0620H 20'0640H 20'0660H 20'0680H 20'06A0H 20'06C0H 20'06E0H Message Object Number Message Object 9 Message Object 10 Message Object 11 Message Object 12 Message Object 13 Message Object 14 Message Object 15 Message Object 16 Message Object 17 Message Object 18 Message Object 19 Message Object 20 Message Object 21 Message Object 22 Message Object 23 Message Object 24 Message Object 25 Message Object 26 Message Object 27 Message Object 28 Message Object 29 Message Object 30 Message Object 31 User's Manual RegSet_X71, V2.0 23-18 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-4 Short Name CAN_ MSGDRLn0 CAN_ MSGDRHn0 CAN_ MSGDRLn4 CAN_ MSGDRHn4 CAN_ MSGARLn CAN_ MSGARHn CAN_ MSGAMRLn CAN_ MSGAMRHn CAN_ MSGCTRLn CAN_ MSGCTRHn CAN_ MSGCFGLn CAN_ MSGCFGHn CAN_ MSGFGCRLn CAN_ MSGFGCRHn Note: n = 0 to 31 Offset Address of Message Object Registers Offset Address 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH Description Message Object n Data Register 0 Low Message Object n Data Register 0 High Message Object n Data Register 4 Low Message Object n Data Register 4 High Message Object n Arbitration Register Low Message Object n Arbitration Register High Message Object n Acceptance Mask Register Low Message Object n Acceptance Mask Register High Message Object n Control Register Low Message Object n Control Register High Message Object n Configuration Register Low Message Object n Configuration Register High Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Message Object n FIFO/Gateway Control 0000H Register Low Message Object n FIFO/Gateway Control 0000H Register High User's Manual RegSet_X71, V2.0 23-19 V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the XC167 in terms of its architecture, its functional units or functions. This helps to quickly find the answer to specific questions about the XC167. This User's Manual consists of two Volumes, "System Units" and "Peripheral Units". For your convenience this keyword index (and also the table of contents) refers to both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]). A Acronyms 1-9 [1] Adapt Mode 6-21 [1] ADC 2-22 [1], 16-1 [2] ADC_CIC, ADC_EIC 16-21 [2] ADC_CON 16-3 [2] ADC_CON1 16-4 [2] ADC_CTR0 16-5 [2] ADC_CTR2 16-7 [2] ADC_CTR2IN 16-7 [2] Address Boundaries 3-15 [1] Mapping 3-3 [1] Segment 6-19 [1] Addressing Modes CoREG Addressing Mode 4-51 [1] DSP Addressing Modes 4-47 [1] Indirect Addressing Modes 4-45 [1] Long Addressing Modes 4-41 [1] Short Addressing Modes 4-39 [1] Alternate Port Functions 7-8 [1] ALU 4-58 [1] Analog/Digital Converter 16-1 [2] Arbitration of conversions 16-16 [2] ASC 19-1 [2] ASCx_EIC, ASCx_RIC 19-35 [2] ASCx_TIC, ASCx_TBIC 19-35 [2] Autobaud Detection 19-27 [2] Error Detection 19-34 [2] Features and Functions 19-1 [2] IrDA Frames 19-8 [2] Register User's Manual i-1 BG 19-22 [2] RBUF 19-12 [2], 19-20 [2] TBUF 19-9 [2], 19-20 [2] Transmit FIFO 19-9 [2] ASCx_BG 19-42 [2] ASCx_CON 19-40 [2] ASCx_FDV 19-43 [2] Auto Scan conversion 16-12 [2] Autobaud Detection 19-27 [2] B BANKSELx 5-33 [1] Baudrate ASC0 19-22 [2] Bootstrap Loader 10-5 [1] CAN 22-56 [2] Bit Handling 4-61 [1] Manipulation Instructions 12-2 [1] protected 2-32 [1], 4-62 [1] reserved 2-16 [1] Block Diagram ITC / PEC 5-3 [1] Bootstrap Loader 6-21 [1], 10-1 [1] Boundaries 3-15 [1] Bus ASC 19-1 [2] CAN 2-25 [1] IIC 2-26 [1], 21-1 [2] Mode Configuration 6-20 [1] SSC 20-1 [2] V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index C Calibration 16-17 [2] CAN acceptance filtering 22-16 [2] analysing mode 22-7 [2] arbitration 22-16 [2] baudrate 22-56 [2] bit timing 22-9 [2], 22-56 [2] bus off recovery sequence 22-4 [2] status bit 22-51 [2] CAN siehe TwinCAN 22-1 [2] error counters 22-55 [2] error handling 22-11 [2] error warning level 22-55 [2] frame counter/time stamp 22-55 [2], 22-58 [2] Interface 2-25 [1] single data transfer 22-23 [2] CAPCOM 2-18 [1] CAPCOM12 2-16 [1] Capture Mode 17-13 [2] Counter Mode 17-8 [2] CAPREL 14-54 [2] Capture Mode GPT1 14-26 [2] GPT2 (CAPREL) 14-46 [2] Capture/Compare Registers 17-10 [2] CC1_DRM, CC2_DRM 17-23 [2] CC1_IOC, CC2_IOC 17-29 [2] CC1_M0-3 17-10 [2] CC1_OUT, CC2_OUT 17-25 [2] CC1_SEE, CC2_SEE 17-28 [2] CC1_SEM, CC2_SEM 17-27 [2] CC1_T01CON 17-5 [2] CC1_T0IC 17-9 [2] CC1_T1IC 17-9 [2] CC2_M4-7 17-11 [2] CC2_T78CON 17-5 [2] CC2_T7IC 17-9 [2] CC2_T8IC 17-9 [2] CC63R 18-40 [2] CC63SR 18-40 [2] CC6xR 18-18 [2] CC6XSR 18-19 [2] CCU6xIC 18-79 [2] CCxIC 17-34 [2] Chip Select Configuration 6-19 [1] Clock generation 2-29 [1] generator modes 6-18 [1] output signal 6-39 [1] CMPMODIF 18-46 [2] CMPSTAT 18-45 [2] Command sequences (Flash) 3-19 [1] Concatenation of Timers 14-22 [2], 14-45 [2] Configuration Address 6-19 [1] Bus Mode 6-20 [1] Chip Select 6-19 [1] default 6-23 [1] PLL 6-18 [1] Reset 6-14 [1] Reset Output 6-22 [1] special modes 6-21 [1] Write Control 6-20 [1] Context Pointer Updating 4-34 [1] Switch 4-33 [1] Switching 5-32 [1] Conversion analog/digital 16-1 [2] Arbitration 16-16 [2] Auto Scan 16-12 [2] timing control 16-18 [2] Count direction 14-6 [2], 14-35 [2] Counter 14-20 [2], 14-43 [2] Counter Mode (GPT1) 14-10 [2], 14-39 [2] CP 4-36 [1] CPU 2-2 [1], 4-1 [1] CPUCON1 4-26 [1] CPUCON2 4-27 [1] i-2 V2.0, 2004-04 User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index CRIC 14-55 [2] CSP 4-38 [1] Error Detection ASC 19-34 [2] SSC 20-14 [2] EXICON 5-37 [1] EXISEL0 5-38 [1] EXISEL1 5-38 [1] External Bus 2-13 [1] Fast interrupts 5-37 [1] Interrupt pulses 5-40 [1] Interrupt source control 5-37 [1] Interrupts 5-35 [1] Interrupts during sleep mode 5-39 [1] D Data Management Unit (Introduction) 2-9 [1] Data Page 4-42 [1] boundaries 3-15 [1] Data SRAM 3-9 [1] Default startup configuration 6-23 [1] Development Support 1-8 [1] Direction count 14-6 [2], 14-35 [2] Disable Interrupt 5-29 [1] Division 4-63 [1] Double-Register Compare 17-22 [2] DP0L, DP0H 7-10 [1] DP1L, DP1H 7-14 [1] DP20 7-82 [1] DP3 7-24 [1], 7-29 [1] DP4 7-41 [1], 22-85 [2] DP6 7-54 [1] DP7 7-65 [1], 22-86 [2] DP9 7-72 [1], 22-88 [2] DPP 4-42 [1] Driver characteristic (ports) 7-4 [1] DSTPx 5-23 [1] Dual-Port RAM 3-9 [1] F Fast external interrupts 5-37 [1] FINT0ADDR 5-16 [1] FINT0CSP 5-17 [1] FINT1ADDR 5-16 [1] FINT1CSP 5-17 [1] Flags 4-57 [1]-4-60 [1] Flash command sequences 3-19 [1] memory 3-11 [1] memory mapping 3-16 [1] waitstates 3-40 [1] FOCON 6-40 [1] Frequency output signal 6-39 [1] FSR 3-32 [1] E EBC Bus Signals 9-3 [1] Memory Table 9-29 [1] EBCMOD0 9-12 [1] Edge characteristic (ports) 7-5 [1] EMUCON 6-48 [1] Enable Interrupt 5-29 [1] End of PEC Interrupt Sub Node 5-28 [1] EOPIC 5-27 [1] Erase command (Flash) 3-21 [1] Error correction 3-25 [1] User's Manual i-3 G Gated timer mode (GPT1) 14-9 [2] Gated timer mode (GPT2) 14-38 [2] GPR 3-6 [1] GPT 2-19 [1] GPT1 14-2 [2] GPT12E_CAPREL 14-54 [2] GPT12E_T2,-T3,-T4 14-29 [2] GPT12E_T2CON 14-15 [2] GPT12E_T2IC,-T3IC,-T4IC 14-30 [2] GPT12E_T3CON 14-4 [2] GPT12E_T4CON 14-15 [2] V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index GPT12E_T5,-T6 14-54 [2] GPT12E_T5CON 14-40 [2] GPT12E_T5IC,-T6IC,-CRIC 14-55 [2] GPT12E_T6CON 14-33 [2] GPT2 14-31 [2] Bit Manipulation 12-2 [1] Pipeline 4-11 [1] protected 12-6 [1] Interface ASC 19-1 [2] CAN 2-25 [1] External Bus 9-1 [1] IIC 2-26 [1], 21-1 [2] SSC 20-1 [2] Interrupt Arbitration 5-4 [1] during sleep mode 5-39 [1] Enable/Disable 5-29 [1] External 5-35 [1] Fast external 5-37 [1] input timing 5-40 [1] Jump Table Cache 5-16 [1] Latency 5-41 [1] Node Sharing 5-34 [1] Priority 5-7 [1] Processing 5-1 [1] RTC 15-12 [2] source control 5-37 [1] Sources 5-12 [1] System 2-8 [1], 5-2 [1] Vectors 5-12 [1] Interrupt Handling CAN transfer 22-6 [2] IP 4-38 [1] IrDA Frames ASC 19-8 [2] IS 18-72 [2] ISR 18-76 [2] ISS 18-75 [2] H Hardware Traps 5-43 [1] I I2C 21-1 [2] IDCHIP 6-64 [1] Idle Mode 6-54 [1] IDMANUF 6-64 [1] IDMEM 6-65 [1] IDPROG 6-65 [1] IDX0, IDX1 4-47 [1] IEN 18-77 [2] IIC 21-1 [2] Programming 21-16 [2] Register Overview 21-12 [2] IIC Interface 2-26 [1] IIC_ADR 21-9 [2] IIC_CFG 21-10 [2] IIC_CON 21-5 [2] IIC_DIC 21-18 [2] IIC_PEIC 21-18 [2] IIC_RTBH 21-11 [2] IIC_RTBL 21-11 [2] IIC_ST 21-7 [2] IMB block diagram 3-37 [1] control functions 3-41 [1] memories address map 3-38 [1] wait states 3-41 [1] IMBCTR 3-41 [1] Incremental Interface Mode (GPT1) 14-11 [2] Indication of reset source 6-46 [1] INP 18-78 [2] Instruction 12-1 [1] User's Manual i-4 L Latency Interrupt, PEC 5-41 [1] LXBus 2-13 [1] M MAH, MAL 4-69 [1] MAR 3-26 [1] Margin check 3-25 [1] V2.0, 2004-04 XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index Master mode IIC Bus 21-12 [2] MCMCTR 18-60 [2] MCMOUT 18-58 [2] MCMOUTS 18-57 [2] MCW 4-66 [1] MDC 4-64 [1] MDH 4-63 [1] MDL 4-64 [1] Memory 2-10 [1] Areas (Data) 3-8 [1] Areas (Program) 3-10 [1] DPRAM 3-9 [1] DSRAM 3-9 [1] External 3-14 [1] Flash 3-11 [1] Program Flash 3-16 [1] PSRAM 3-11 [1] MODCTR 18-49 [2] MRW 4-72 [1] MSW 4-70 [1] Multimaster mode IIC Bus 21-12 [2] Multiplication 4-63 [1] Watchdog 6-22 [1], 6-38 [1] P P0L, P0H 7-9 [1] P1L, P1H 7-13 [1] P3 7-24 [1], 7-29 [1] P4 7-41 [1] P5 7-50 [1], 7-51 [1] P8 7-54 [1], 7-65 [1], 7-72 [1], 7-82 [1] PEC 2-10 [1], 5-18 [1] Latency 5-41 [1] Transfer Count 5-19 [1] PEC pointers 3-7 [1] PECCx 5-19 [1] PECISNC 5-27 [1] PECSEGx 5-23 [1] Peripheral Event Controller --> PEC 5-18 [1] Register Set 23-1 [2] Summary 2-14 [1] Phase Locked Loop (->PLL) 6-26 [1] PICON 7-2 [1] Pins 8-1 [1] Pipeline 4-11 [1] PLL 6-18 [1], 6-26 [1] PLL_IC 6-38 [1] PLLCON 6-32 [1] POCON* 7-6 [1] Port 2-27 [1] Ports Alternate Port Functions 7-8 [1] Driver characteristic 7-4 [1] Edge characteristic 7-5 [1] Power Management 2-29 [1], 6-54 [1] PROCON 3-28 [1] Program Management Unit (Introduction) 2-9 [1] Programming command (Flash) 3-21 [1] Protected Bits 2-32 [1], 4-62 [1] instruction 12-6 [1] Protection commands (Flash) 3-23 [1] i-5 V2.0, 2004-04 N NMI 5-1 [1], 5-48 [1] Noise filter (Ext. Interrupts) 5-39 [1] O OCDS Requests 5-40 [1] ODP3 7-25 [1], 7-30 [1] ODP4 7-42 [1] ODP6 7-55 [1] ODP7 7-66 [1] ODP9 7-73 [1] ONES 4-74 [1] Open Drain Mode 7-3 [1] OPSEN 6-49 [1] Oscillator circuitry 6-27 [1], 6-29 [1] measurement 6-27 [1], 6-29 [1] User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index features (Flash) 3-27 [1] PSLR 18-68 [2] PSW 4-57 [1] Address 6-19 [1] boundaries 3-15 [1] Segmentation 4-37 [1] Self-calibration 16-17 [2] Serial Interface 2-23 [1], 2-24 [1] ASC 19-1 [2] Asynchronous 19-5 [2] CAN 2-25 [1] IIC 2-26 [1], 21-1 [2] SSC 20-1 [2] Synchronous 19-19 [2] SFR 3-5 [1] Sharing Interrupt Nodes 5-34 [1] Slave mode IIC Bus 21-13 [2] Sleep mode 6-56 [1] Software Traps 5-43 [1] Source Interrupt 5-12 [1] Reset 6-46 [1] SP 4-54 [1] Special operation modes (config.) 6-21 [1] SPSEG 4-54 [1] SRAM Data 3-9 [1] SRCPx 5-23 [1] SSC 20-1 [2] Baudrate generation 20-12 [2] Block diagram 20-3 [2] Continous transfer operation 20-12 [2] Error detection 20-14 [2] Full duplex operation 20-8 [2] General Operation 20-1 [2] Half duplex operation 20-11 [2] Interrupts 20-14 [2] SSCx_CON 20-4 [2], 20-5 [2] Stack 3-12 [1], 4-53 [1] Startup Configuration 6-14 [1] STKOV 4-56 [1] STKUN 4-56 [1] SYSCON0 6-43 [1] i-6 V2.0, 2004-04 Q QR0 4-46 [1] QR1 4-46 [1] QX0, QX1 4-48 [1] R RAM data SRAM 3-9 [1] dual ported 3-9 [1] program/data 3-11 [1] status after reset 6-7 [1] Real Time Clock (->RTC) 2-21 [1], 15-1 [2] Register Areas 3-4 [1] Register map TwinCAN module 22-47 [2] Register Table LXBUS Peripherals 23-16 [2] PD+BUS Peripherals 23-1 [2] RELH, RELL 15-9 [2] Reserved bits 2-16 [1] Reset 6-2 [1] Configuration 6-14 [1] Output 6-9 [1] Source indication 6-46 [1] Values 6-6 [1] RSTCFG 6-16 [1] RSTCON 6-24 [1] RTC 2-21 [1], 15-1 [2] RTC_CON 15-5 [2] RTC_IC 15-13 [2] RTC_ISNC 15-13 [2] RTCH, RTCL 15-8 [2] S SCUSLC 6-52 [1] SCUSLS 6-51 [1] Security features (Flash) 3-27 [1] Segment User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index SYSCON1 6-44 [1] SYSCON3 6-58 [1] SYSSTAT 6-45 [1] TRPCTR 18-63 [2] TwinCAN FIFO base object 22-24 [2] circular buffer 22-26 [2] configuration 22-73 [2] for CAN messages 22-24 [2] gateway control 22-73 [2] slave objects 22-26 [2] frames counter 22-8 [2] handling 22-17 [2] gateway configuration 22-73 [2] normal mode 22-29 [2] shared mode 22-36 [2] with FIFO 22-33 [2] initialization 22-40 [2] interrupts indication/INTID 22-13 [2], 22-53 [2] node pointer/request compressor 22-5 [2] loop-back mode 22-44 [2] message handling 22-15 [2] FIFO 22-24 [2] gateway overview 22-28 [2] gateway+FIFO 22-33 [2] normal gateway 22-29 [2] shared gateway 22-36 [2] transfer control 22-41 [2] message interrupts 22-13 [2] message object configuration 22-71 [2] control bits 22-68 [2] interrupt indication 22-13 [2] interrupts 22-13 [2] register description 22-64 [2] transfer handling 22-17 [2] node control 22-7 [2] node interrupts 22-11 [2], 22-12 [2] node selection 22-71 [2] overview 22-1 [2] i-7 V2.0, 2004-04 T T0IC 17-9 [2] T12 18-6 [2] T12DTC 18-23 [2] T12MSEL 18-20 [2] T12PR 18-6 [2] T13 18-31 [2] T13PR 18-31 [2] T1IC 17-9 [2] T2, T3, T4 14-29 [2] T2CON 14-15 [2] T2IC, T3IC, T4IC 14-30 [2] T3CON 14-4 [2] T4CON 14-15 [2] T5, T6 14-54 [2] T5CON 14-40 [2] T5IC, T6IC 14-55 [2] T6CON 14-33 [2] T7IC 17-9 [2] T8IC 17-9 [2] TCTR0 18-41 [2] TCTR2 18-43 [2] TCTR4 18-44 [2] TFR 5-45 [1] Timer 14-2 [2], 14-31 [2] Auxiliary Timer 14-15 [2], 14-40 [2] Concatenation 14-22 [2], 14-45 [2] Core Timer 14-4 [2], 14-33 [2] Counter Mode (GPT1) 14-10 [2], 14-39 [2] Gated Mode (GPT1) 14-9 [2] Gated Mode (GPT2) 14-38 [2] Incremental Interface Mode (GPT1) 14-11 [2] Mode (GPT1) 14-8 [2] Mode (GPT2) 14-37 [2] Tools 1-8 [1] Transmit FIFO ASC 19-9 [2] Traps 5-43 [1] User's Manual XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index register map 22-47 [2] registers (global) receive interrupt pending 22-80 [2] transmit interrupt pending 22-81 [2] registers (message specific) acceptance mask 22-67 [2] arbitration (identifier) 22-66 [2] configuration 22-71 [2] control 22-68 [2] data 22-64 [2] registers (node specific) bit timing 22-56 [2] control 22-49 [2] error counter 22-55 [2] frame counter 22-58 [2] global interrupt node pointer 22-61 [2] interrupt pending 22-53 [2] INTID mask 22-62 [2] status 22-51 [2] single transmission 22-45 [2] single-shot mode 22-23 [2] transfer interrupts 22-6 [2] TwinCAN Registers (short names) ABTRH 22-56 [2] ABTRL 22-56 [2] ACR 22-49 [2] AECNTH 22-54 [2] AECNTL 22-54 [2] AFCRH 22-58 [2] AFCRL 22-58 [2] AGINP 22-61 [2] AIMR0H 22-62 [2] AIMR0L 22-62 [2] AIMR4 22-63 [2] AIR 22-53 [2] ASR 22-51 [2] BBTRH 22-56 [2] BBTRL 22-56 [2] BCR 22-49 [2] BECNTH 22-54 [2] BECNTL 22-54 [2] BFCRH 22-58 [2] User's Manual i-8 BFCRL 22-58 [2] BGINP 22-61 [2] BIMR0H 22-62 [2] BIMR0L 22-62 [2] BIMR4 22-63 [2] BIR 22-53 [2] BSR 22-51 [2] MSGAMRHn 22-67 [2] MSGAMRLn 22-67 [2] MSGARHn 22-66 [2] MSGARLn 22-66 [2] MSGCFGHn 22-71 [2] MSGCFGLn 22-71 [2] MSGCTRHn 22-68 [2] MSGCTRLn 22-68 [2] MSGDRH0 22-64 [2] MSGDRH4 22-65 [2] MSGDRL0 22-64 [2] MSGDRL4 22-65 [2] MSGFGCRHn 22-74 [2] MSGFGCRLn 22-74 [2] RXIPNDH 22-80 [2] RXIPNDL 22-80 [2] TXIPNDH 22-81 [2] TXIPNDL 22-81 [2] V VECSEG 5-11 [1] W Waitstates Flash 3-40 [1] Watchdog 2-26 [1], 6-59 [1] after reset 6-7 [1] Oscillator 6-22 [1], 6-38 [1] WDT 6-60 [1] WDTCON 6-62 [1] Z ZEROS 4-74 [1] V2.0, 2004-04 www.infineon.com Published by Infineon Technologies AG |
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